prescale_counter.dly

学习Xilinx公司开发软件ISE的基础资料

Release 5.1.02i - Par F.25
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Sat Dec 28 15:56:14 2002

File: prescale_counter.dly

 The 20 Worst Net Delays are:
-------------------------------
| Max Delay (ns)  | Netname   |
-------------------------------
   3.651            reset_ibuf
   2.573            counter<27>
   2.506            counter<30>
   2.448            counter<23>
   2.433            counter<26>
   2.370            counter<31>
   2.326            counter<17>
   2.203            counter<9>
   2.201            counter<29>
   2.159            counter<22>
   2.116            counter<0>
   2.108            _n00021_1
   1.921            counter<28>
   1.919            counter<24>
   1.906            counter<5>
   1.875            _n0002
   1.852            counter<4>
   1.841            counter<2>
   1.827            counter<25>
   1.806            counter<19>
---------------------------------

-------------------------------------------------------------------------------
                               Net Delays
-------------------------------------------------------------------------------

GLOBAL_LOGIC0
   PWR_GND_0.Y
         0.780  counter<3>.G1

GLOBAL_LOGIC1
   PWR_VCC_0.X
         0.534  counter<3>.F1

_n0001<22>
   counter<25>.X
         1.707  counter<24>.BY

_n0001<8>
   counter<11>.X
         1.197  counter<2>.BY

_n0002
   counter<2>.Y
         1.471  counter<11>.CE
         1.545  counter<12>.CE
         1.574  counter<14>.CE
         1.397  counter<16>.CE
         1.666  counter<18>.CE
         1.875  counter<20>.CE
         1.860  counter<22>.CE
         0.862  counter<2>.CE

_n00021_1
   counter<24>.Y
         1.274  counter<3>.CE
         1.272  counter<4>.CE
         1.222  counter<6>.CE
         1.028  counter<8>.CE
         1.880  counter<25>.CE
         2.044  counter<26>.CE
         2.021  counter<28>.CE
         2.108  counter<30>.CE
         1.028  counter<24>.CE

clk_bufgp
   clk_bufgp/BUFG.OUT
         0.406  counter<3>.CLK
         0.358  counter<4>.CLK
         0.406  counter<6>.CLK
         0.358  counter<8>.CLK
         0.399  counter<11>.CLK
         0.399  counter<12>.CLK
         0.399  counter<14>.CLK
         0.399  counter<16>.CLK
         0.400  counter<18>.CLK
         0.400  counter<20>.CLK
         0.400  counter<22>.CLK
         0.400  counter<25>.CLK
         0.411  counter<26>.CLK
         0.411  counter<28>.CLK
         0.411  counter<30>.CLK
         0.358  counter<2>.CLK
         0.358  counter<24>.CLK
         0.358  counter<0>.CLK

clk_bufgp/IBUFG
   clk.GCLKOUT
         0.000  clk_bufgp/BUFG.IN

counter<0>
   counter<0>.XQ
         1.424  counter_out<0>.O
         0.280  counter<2>.G3
         0.695  counter<24>.G3
         1.967  counter<0>.BX
         2.116  counter<0>.G1

counter<10>
   counter<2>.YQ
         1.507  counter_out<10>.O
         1.101  counter<11>.F2

counter<11>
   counter<11>.YQ
         1.524  counter_out<11>.O
         0.463  counter<11>.G4

counter<12>
   counter<12>.XQ
         1.183  counter_out<12>.O
         0.693  counter<12>.F1

counter<13>
   counter<12>.YQ
         1.568  counter_out<13>.O
         0.460  counter<12>.G3

counter<14>
   counter<14>.XQ
         1.499  counter_out<14>.O
         0.565  counter<14>.F2

counter<15>
   counter<14>.YQ
         1.191  counter_out<15>.O
         0.463  counter<14>.G4

counter<16>
   counter<16>.XQ
         1.643  counter_out<16>.O
         0.693  counter<16>.F1

counter<17>
   counter<16>.YQ
         2.326  counter_out<17>.O
         0.421  counter<16>.G3

counter<18>
   counter<18>.XQ
         1.564  counter_out<18>.O
         0.565  counter<18>.F2

counter<19>
   counter<18>.YQ
         1.806  counter_out<19>.O
         0.460  counter<18>.G3

counter<1>
   counter<0>.YQ
         1.753  counter_out<1>.O
         0.277  counter<2>.G4
         0.685  counter<24>.G4
         1.423  counter<0>.G2

counter<20>
   counter<20>.XQ
         1.759  counter_out<20>.O
         0.565  counter<20>.F2

counter<21>
   counter<20>.YQ
         1.443  counter_out<21>.O
         0.460  counter<20>.G3

counter<22>
   counter<22>.XQ
         2.159  counter_out<22>.O
         0.693  counter<22>.F1

counter<23>
   counter<22>.YQ
         2.448  counter_out<23>.O
         0.441  counter<22>.G3

counter<24>
   counter<24>.YQ
         1.919  counter_out<24>.O
         1.206  counter<25>.F3

counter<25>
   counter<25>.YQ
         1.827  counter_out<25>.O
         0.463  counter<25>.G4

counter<26>
   counter<26>.XQ
         2.433  counter_out<26>.O
         0.693  counter<26>.F1

counter<27>
   counter<26>.YQ
         2.573  counter_out<27>.O
         0.441  counter<26>.G3

counter<28>
   counter<28>.XQ
         1.921  counter_out<28>.O
         0.693  counter<28>.F1

counter<29>
   counter<28>.YQ
         2.201  counter_out<29>.O
         0.738  counter<28>.G3

counter<2>
   counter<2>.XQ
         1.841  counter_out<2>.O
         0.487  counter<3>.F4

counter<30>
   counter<30>.XQ
         2.506  counter_out<30>.O
         0.703  counter<30>.F1

counter<31>
   counter<30>.YQ
         2.370  counter_out<31>.O
         0.460  counter<30>.G3

counter<3>
   counter<3>.YQ
         1.380  counter_out<3>.O
         0.460  counter<3>.G3

counter<4>
   counter<4>.XQ
         1.852  counter_out<4>.O
         0.580  counter<4>.F2

counter<5>
   counter<4>.YQ
         1.906  counter_out<5>.O
         0.760  counter<4>.G1

counter<6>
   counter<6>.XQ
         0.943  counter_out<6>.O
         0.693  counter<6>.F1

counter<7>
   counter<6>.YQ
         0.943  counter_out<7>.O
         0.460  counter<6>.G3

counter<8>
   counter<8>.XQ
         0.949  counter_out<8>.O
         0.577  counter<8>.F2

counter<9>
   counter<8>.YQ
         2.203  counter_out<9>.O
         0.922  counter<8>.G3

madd__n0001_inst_cy_1
   counter<3>.COUT
         0.000  counter<4>.CIN

madd__n0001_inst_cy_11
   counter<12>.COUT
         0.000  counter<14>.CIN

madd__n0001_inst_cy_13
   counter<14>.COUT
         0.000  counter<16>.CIN

madd__n0001_inst_cy_15
   counter<16>.COUT
         0.000  counter<18>.CIN

madd__n0001_inst_cy_17
   counter<18>.COUT
         0.000  counter<20>.CIN

madd__n0001_inst_cy_19
   counter<20>.COUT
         0.000  counter<22>.CIN

madd__n0001_inst_cy_21
   counter<22>.COUT
         0.000  counter<25>.CIN

madd__n0001_inst_cy_23
   counter<25>.COUT
         0.000  counter<26>.CIN

madd__n0001_inst_cy_25
   counter<26>.COUT
         0.000  counter<28>.CIN

madd__n0001_inst_cy_27
   counter<28>.COUT
         0.000  counter<30>.CIN

madd__n0001_inst_cy_3
   counter<4>.COUT
         0.000  counter<6>.CIN

madd__n0001_inst_cy_5
   counter<6>.COUT
         0.000  counter<8>.CIN

madd__n0001_inst_cy_7
   counter<8>.COUT
         0.000  counter<11>.CIN

madd__n0001_inst_cy_9
   counter<11>.COUT
         0.000  counter<12>.CIN

madd__n0001_inst_lut2_0
   counter<3>.X
         0.705  counter<2>.BX

reset_ibuf
   reset.I
         2.546  counter<3>.SR
         2.760  counter<4>.SR
         3.323  counter<6>.SR
         3.226  counter<8>.SR
         3.573  counter<11>.SR
         3.584  counter<12>.SR
         3.614  counter<14>.SR
         3.651  counter<16>.SR
         3.625  counter<18>.SR
         3.594  counter<20>.SR
         1.644  counter<22>.SR
         1.544  counter<25>.SR
         1.518  counter<26>.SR
         1.538  counter<28>.SR
         1.635  counter<30>.SR
         3.353  counter<2>.SR
         3.226  counter<24>.SR
         3.371  counter<0>.SR