prescale_counter.twr

学习Xilinx公司开发软件ISE的基础资料

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Release 5.1.02i - Trace F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -quiet -e 3 -l 3 -xml prescale_counter
prescale_counter.ncd -o prescale_counter.twr prescale_counter.pcf

Design file:              prescale_counter.ncd
Physical constraint file: prescale_counter.pcf
Device,speed:             xcv100e,-6 (PRODUCTION 1.68 2002-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk"  5 nS   HIGH 50.000000 % ;

 63 items analyzed, 0 timing errors detected.
 Minimum period is   4.950ns.
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================================================================================
Timing constraint: TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP 
"upper_counter" TS_clk * 4.000 ;

 465 items analyzed, 0 timing errors detected.
 Maximum delay is   7.256ns.
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================================================================================
Timing constraint: OFFSET = OUT 10 nS  AFTER COMP "clk" ;

 32 items analyzed, 0 timing errors detected.
 Minimum allowable offset is   9.777ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
---------------+------------+
               | clk (edge) |
Destination Pad|   to PAD   |
---------------+------------+
counter_out<0> |    8.575(R)|
counter_out<10>|    8.658(R)|
counter_out<11>|    8.716(R)|
counter_out<12>|    8.375(R)|
counter_out<13>|    8.760(R)|
counter_out<14>|    8.691(R)|
counter_out<15>|    8.383(R)|
counter_out<16>|    8.835(R)|
counter_out<17>|    9.518(R)|
counter_out<18>|    8.757(R)|
counter_out<19>|    8.999(R)|
counter_out<1> |    8.904(R)|
counter_out<20>|    8.952(R)|
counter_out<21>|    8.636(R)|
counter_out<22>|    9.352(R)|
counter_out<23>|    9.641(R)|
counter_out<24>|    9.070(R)|
counter_out<25>|    9.020(R)|
counter_out<26>|    9.637(R)|
counter_out<27>|    9.777(R)|
counter_out<28>|    9.125(R)|
counter_out<29>|    9.405(R)|
counter_out<2> |    8.992(R)|
counter_out<30>|    9.710(R)|
counter_out<31>|    9.574(R)|
counter_out<3> |    8.579(R)|
counter_out<4> |    9.003(R)|
counter_out<5> |    9.057(R)|
counter_out<6> |    8.142(R)|
counter_out<7> |    8.142(R)|
counter_out<8> |    8.100(R)|
counter_out<9> |    9.354(R)|
---------------+------------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.256|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 560 paths, 0 nets, and 122 connections (87.1% coverage)

Design statistics:
   Minimum period:   7.256ns (Maximum frequency: 137.817MHz)
   Maximum path delay from/to any node:   7.256ns
   Minimum output required time after clock:   9.777ns


Analysis completed Sat Dec 28 15:56:17 2002
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