dpram_core.edn

学习Xilinx公司开发软件ISE的基础资料

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2002 11 5 20 35 33)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 5.1i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2002 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_reg_inputsb = 0 ")
       (comment "c_reg_inputsa = 0 ")
       (comment "c_has_ndb = 0 ")
       (comment "c_has_nda = 0 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_has_rfdb = 0 ")
       (comment "c_has_rfda = 0 ")
       (comment "c_ywea_is_high = 1 ")
       (comment "c_yena_is_high = 1 ")
       (comment "InstanceName = dpram_core ")
       (comment "c_yclka_is_rising = 1 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_family = virtex2p ")
       (comment "c_ysinita_is_high = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_width_b = 16 ")
       (comment "c_width_a = 16 ")
       (comment "c_sinita_value = 0 ")
       (comment "c_sinitb_value = 0 ")
       (comment "c_limit_data_pitch = 18 ")
       (comment "c_write_modeb = 0 ")
       (comment "c_write_modea = 0 ")
       (comment "c_has_rdyb = 0 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_rdya = 0 ")
       (comment "c_addra_width = 4 ")
       (comment "c_addrb_width = 4 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_default_data = 0 ")
       (comment "c_pipe_stages_b = 0 ")
       (comment "c_yweb_is_high = 1 ")
       (comment "c_yenb_is_high = 1 ")
       (comment "c_pipe_stages_a = 0 ")
       (comment "c_yclkb_is_rising = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_ysinitb_is_high = 1 ")
       (comment "c_has_web = 1 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_has_sinitb = 0 ")
       (comment "c_has_wea = 1 ")
       (comment "c_has_sinita = 0 ")
       (comment "c_has_dinb = 1 ")
       (comment "c_has_dina = 1 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_has_enb = 0 ")
       (comment "c_has_ena = 0 ")
       (comment "c_depth_b = 16 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_depth_a = 16 ")
       (comment "c_has_doutb = 1 ")
       (comment "c_has_douta = 1 ")
       (comment "c_yprimitive_type = 16kx1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB16_S18_S18 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WEA (direction INPUT))
                   (port ENA (direction INPUT))
                   (port SSRA (direction INPUT))
                   (port CLKA (direction INPUT))
                   (port (rename DIA_0_ "DIA<0>") (direction INPUT))
                   (port (rename DIA_1_ "DIA<1>") (direction INPUT))
                   (port (rename DIA_2_ "DIA<2>") (direction INPUT))
                   (port (rename DIA_3_ "DIA<3>") (direction INPUT))
                   (port (rename DIA_4_ "DIA<4>") (direction INPUT))
                   (port (rename DIA_5_ "DIA<5>") (direction INPUT))
                   (port (rename DIA_6_ "DIA<6>") (direction INPUT))
                   (port (rename DIA_7_ "DIA<7>") (direction INPUT))
                   (port (rename DIA_8_ "DIA<8>") (direction INPUT))
                   (port (rename DIA_9_ "DIA<9>") (direction INPUT))
                   (port (rename DIA_10_ "DIA<10>") (direction INPUT))
                   (port (rename DIA_11_ "DIA<11>") (direction INPUT))
                   (port (rename DIA_12_ "DIA<12>") (direction INPUT))
                   (port (rename DIA_13_ "DIA<13>") (direction INPUT))
                   (port (rename DIA_14_ "DIA<14>") (direction INPUT))
                   (port (rename DIA_15_ "DIA<15>") (direction INPUT))
                   (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
                   (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
                   (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
                   (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
                   (port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
                   (port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
                   (port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
                   (port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
                   (port (rename DOA_8_ "DOA<8>") (direction OUTPUT))
                   (port (rename DOA_9_ "DOA<9>") (direction OUTPUT))
                   (port (rename DOA_10_ "DOA<10>") (direction OUTPUT))
                   (port (rename DOA_11_ "DOA<11>") (direction OUTPUT))
                   (port (rename DOA_12_ "DOA<12>") (direction OUTPUT))
                   (port (rename DOA_13_ "DOA<13>") (direction OUTPUT))
                   (port (rename DOA_14_ "DOA<14>") (direction OUTPUT))
                   (port (rename DOA_15_ "DOA<15>") (direction OUTPUT))
                   (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
                   (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
                   (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
                   (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
                   (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
                   (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
                   (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
                   (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
                   (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
                   (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
                   (port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
                   (port (rename DIPA_1_ "DIPA<1>") (direction INPUT))
                   (port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
                   (port (rename DOPA_1_ "DOPA<1>") (direction OUTPUT))
                   (port WEB (direction INPUT))
                   (port ENB (direction INPUT))
                   (port SSRB (direction INPUT))
                   (port CLKB (direction INPUT))
                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
                   (port (rename DIB_4_ "DIB<4>") (direction INPUT))
                   (port (rename DIB_5_ "DIB<5>") (direction INPUT))
                   (port (rename DIB_6_ "DIB<6>") (direction INPUT))
                   (port (rename DIB_7_ "DIB<7>") (direction INPUT))
                   (port (rename DIB_8_ "DIB<8>") (direction INPUT))
                   (port (rename DIB_9_ "DIB<9>") (direction INPUT))
                   (port (rename DIB_10_ "DIB<10>") (direction INPUT))
                   (port (rename DIB_11_ "DIB<11>") (direction INPUT))
                   (port (rename DIB_12_ "DIB<12>") (direction INPUT))
                   (port (rename DIB_13_ "DIB<13>") (direction INPUT))
                   (port (rename DIB_14_ "DIB<14>") (direction INPUT))
                   (port (rename DIB_15_ "DIB<15>") (direction INPUT))
                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
                   (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
                   (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
                   (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
                   (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
                   (port (rename DOB_8_ "DOB<8>") (direction OUTPUT))
                   (port (rename DOB_9_ "DOB<9>") (direction OUTPUT))
                   (port (rename DOB_10_ "DOB<10>") (direction OUTPUT))
                   (port (rename DOB_11_ "DOB<11>") (direction OUTPUT))
                   (port (rename DOB_12_ "DOB<12>") (direction OUTPUT))
                   (port (rename DOB_13_ "DOB<13>") (direction OUTPUT))
                   (port (rename DOB_14_ "DOB<14>") (direction OUTPUT))
                   (port (rename DOB_15_ "DOB<15>") (direction OUTPUT))
                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
                   (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
                   (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
                   (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
                   (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
                   (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
                   (port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
                   (port (rename DIPB_1_ "DIPB<1>") (direction INPUT))
                   (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
                   (port (rename DOPB_1_ "DOPB<1>") (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell dpram_core
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename addra_3_ "addra<3>") (direction INPUT))
   (port ( rename addra_2_ "addra<2>") (direction INPUT))
   (port ( rename addra_1_ "addra<1>") (direction INPUT))
   (port ( rename addra_0_ "addra<0>") (direction INPUT))
   (port ( rename addrb_3_ "addrb<3>") (direction INPUT))
   (port ( rename addrb_2_ "addrb<2>") (direction INPUT))
   (port ( rename addrb_1_ "addrb<1>") (direction INPUT))
   (port ( rename addrb_0_ "addrb<0>") (direction INPUT))
   (port ( rename clka "clka") (direction INPUT))
   (port ( rename clkb "clkb") (direction INPUT))
   (port ( rename dina_15_ "dina<15>") (direction INPUT))
   (port ( rename dina_14_ "dina<14>") (direction INPUT))
   (port ( rename dina_13_ "dina<13>") (direction INPUT))
   (port ( rename dina_12_ "dina<12>") (direction INPUT))
   (port ( rename dina_11_ "dina<11>") (direction INPUT))
   (port ( rename dina_10_ "dina<10>") (direction INPUT))
   (port ( rename dina_9_ "dina<9>") (direction INPUT))
   (port ( rename dina_8_ "dina<8>") (direction INPUT))
   (port ( rename dina_7_ "dina<7>") (direction INPUT))
   (port ( rename dina_6_ "dina<6>") (direction INPUT))
   (port ( rename dina_5_ "dina<5>") (direction INPUT))
   (port ( rename dina_4_ "dina<4>") (direction INPUT))
   (port ( rename dina_3_ "dina<3>") (direction INPUT))
   (port ( rename dina_2_ "dina<2>") (direction INPUT))
   (port ( rename dina_1_ "dina<1>") (direction INPUT))
   (port ( rename dina_0_ "dina<0>") (direction INPUT))
   (port ( rename dinb_15_ "dinb<15>") (direction INPUT))
   (port ( rename dinb_14_ "dinb<14>") (direction INPUT))
   (port ( rename dinb_13_ "dinb<13>") (direction INPUT))
   (port ( rename dinb_12_ "dinb<12>") (direction INPUT))
   (port ( rename dinb_11_ "dinb<11>") (direction INPUT))
   (port ( rename dinb_10_ "dinb<10>") (direction INPUT))
   (port ( rename dinb_9_ "dinb<9>") (direction INPUT))
   (port ( rename dinb_8_ "dinb<8>") (direction INPUT))
   (port ( rename dinb_7_ "dinb<7>") (direction INPUT))
   (port ( rename dinb_6_ "dinb<6>") (direction INPUT))
   (port ( rename dinb_5_ "dinb<5>") (direction INPUT))
   (port ( rename dinb_4_ "dinb<4>") (direction INPUT))
   (port ( rename dinb_3_ "dinb<3>") (direction INPUT))
   (port ( rename dinb_2_ "dinb<2>") (direction INPUT))
   (port ( rename dinb_1_ "dinb<1>") (direction INPUT))
   (port ( rename dinb_0_ "dinb<0>") (direction INPUT))
   (port ( rename wea "wea") (direction INPUT))
   (port ( rename web "web") (direction INPUT))
   (port ( rename douta_15_ "douta<15>") (direction OUTPUT))
   (port ( rename douta_14_ "douta<14>") (direction OUTPUT))
   (port ( rename douta_13_ "douta<13>") (direction OUTPUT))
   (port ( rename douta_12_ "douta<12>") (direction OUTPUT))
   (port ( rename douta_11_ "douta<11>") (direction OUTPUT))
   (port ( rename douta_10_ "douta<10>") (direction OUTPUT))
   (port ( rename douta_9_ "douta<9>") (direction OUTPUT))
   (port ( rename douta_8_ "douta<8>") (direction OUTPUT))
   (port ( rename douta_7_ "douta<7>") (direction OUTPUT))
   (port ( rename douta_6_ "douta<6>") (direction OUTPUT))
   (port ( rename douta_5_ "douta<5>") (direction OUTPUT))
   (port ( rename douta_4_ "douta<4>") (direction OUTPUT))
   (port ( rename douta_3_ "douta<3>") (direction OUTPUT))
   (port ( rename douta_2_ "douta<2>") (direction OUTPUT))
   (port ( rename douta_1_ "douta<1>") (direction OUTPUT))
   (port ( rename douta_0_ "douta<0>") (direction OUTPUT))
   (port ( rename doutb_15_ "doutb<15>") (direction OUTPUT))
   (port ( rename doutb_14_ "doutb<14>") (direction OUTPUT))
   (port ( rename doutb_13_ "doutb<13>") (direction OUTPUT))
   (port ( rename doutb_12_ "doutb<12>") (direction OUTPUT))
   (port ( rename doutb_11_ "doutb<11>") (direction OUTPUT))
   (port ( rename doutb_10_ "doutb<10>") (direction OUTPUT))
   (port ( rename doutb_9_ "doutb<9>") (direction OUTPUT))
   (port ( rename doutb_8_ "doutb<8>") (direction OUTPUT))
   (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT))
   (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT))
   (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT))
   (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT))
   (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT))
   (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT))
   (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT))
   (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT))