top.syr

学习Xilinx公司开发软件ISE的基础资料

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.70 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report
     6.1) Device utilization summary
     6.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : top.prj
Input Format                       : VERILOG
Ignore Synthesis Constraint File   : NO
Verilog Search Path                : 
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : top
Output Format                      : NGC
Target Device                      : xc2vp50-6ff1152

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Top module area constraint         : 100
Top module allowed area overflow   : 5

---- Other Options
read_cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "top.prj"
Compiling include file "dpram_core.v"
Module <dpram_core> compiled
Compiling include file "top.v"
Module <top> compiled
Compiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <top.prj> succeeded.
 
WARNING:Xst:878 - dpram_core.v line 140: Unrecognized directive. Ignoring.
 
Analyzing module <dpram_core>.
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
 
Analyzing top module <top>.
Module <top> is correct for synthesis.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <top>.
    Related source file is top.v.
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "dpram_core.ngo" is up to date.
Loading core <dpram_core> for timing and area information for instance <dpram_inst>.

Library "J:/eda/Xilinx/data/librtl.xst" Consulted

Optimizing unit <top> ...

Mapping all equations...
Loading device for application Xst from file '2vp50.nph' in environment J:/eda/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Output File Name               : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : NO
Macro Generator                    : macro+

Design Statistics
# IOs                              : 76

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# RAMS                             : 1
#      RAMB16_S18_S18              : 1
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 74
#      IBUF                        : 42
#      OBUF                        : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp50ff1152-6 

 Number of bonded IOBs:                 74  out of    756     9%  
 Number of BRAMs:                        1  out of    264     0%  
 Number of GCLKs:                        2  out of     16    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkb                               | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 1.742ns
   Maximum output required time after clock: 8.066ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkb'
Offset:              1.742ns (Levels of Logic = 1)
  Source:            clka
  Destination:       dpram_inst/B5
  Destination Clock: clkb rising

  Data Path: clka to dpram_inst/B5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O            1   1.502   0.240  clka_BUFGP (clka_BUFGP)
     begin scope: 'dpram_inst'
     RAMB16_S18_S18:CLKA        0.000          B5
    ----------------------------------------
    Total                      1.742ns (1.502ns logic, 0.240ns route)
                                       (86.2% logic, 13.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkb'
Offset:              8.066ns (Levels of Logic = 1)
  Source:            dpram_inst/B5
  Destination:       doutb<15>
  Source Clock:      clkb rising

  Data Path: dpram_inst/B5 to doutb<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S18_S18:CLKB->DOB15    1   2.655   0.240  B5 (doutb<15>)
     end scope: 'dpram_inst'
     OBUF:I->O                 5.171          doutb_15_OBUF (doutb<15>)
    ----------------------------------------
    Total                      8.066ns (7.826ns logic, 0.240ns route)
                                       (97.0% logic, 3.0% route)

=========================================================================
CPU : 8.16 / 9.17 s | Elapsed : 9.00 / 9.00 s
 
--> 

Total memory usage is 152056 kilobytes