det_clock.tlg

来自「学习Xilinx公司开发软件ISE的基础资料」· TLG 代码 · 共 6 行

Selecting top level module det_clock
Synthesizing module det_clock
@W: CL190 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Optimizing register bit cnt[2] to a constant 0
@W: CL171 :"C:\prj\cpld_detect_error\syn\det_clock.v":21:0:21:5|Pruning Register bit <2> of cnt[2:0]