det_clock.prf

来自「学习Xilinx公司开发软件ISE的基础资料」· PRF 代码 · 共 13 行

#
# Logical Preferences generated for Lucent by Synplify 7.3.5, Build 222R.
#

# Period Constraints
FREQUENCY PORT "clk_66M" 1.0 MHz;
# Output Constraints
# Input Constraints

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.