virtex.vhd

学习Xilinx公司开发软件ISE的基础资料

attribute black_box_tri_pins of OBUFT_HSTL_III : component is "O";
component OBUFT_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_HSTL_IV : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV : component is "O";
component OBUFT_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_LVCMOS2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS2 : component is "O";
component OBUFT_PCI33_3
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_PCI33_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI33_3 : component is "O";
component OBUFT_PCI33_5
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_PCI33_5 : component is true;
attribute black_box_tri_pins of OBUFT_PCI33_5 : component is "O";
component OBUFT_PCI66_3
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_PCI66_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI66_3 : component is "O";
component OBUFT_SSTL2_I
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_SSTL2_I : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_I : component is "O";
component OBUFT_SSTL2_II
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_SSTL2_II : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_II : component is "O";
component OBUFT_SSTL3_I
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_SSTL3_I : component is true;
attribute black_box_tri_pins of OBUFT_SSTL3_I : component is "O";
component OBUFT_SSTL3_II
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_SSTL3_II : component is true;
attribute black_box_tri_pins of OBUFT_SSTL3_II : component is "O";
component OBUFT_S_12
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_S_12 : component is "O";
component OBUFT_S_16
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_S_16 : component is "O";
component OBUFT_S_2
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_S_2 : component is "O";
component OBUFT_S_24
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_24 : component is true;
attribute black_box_tri_pins of OBUFT_S_24 : component is "O";
component OBUFT_S_4
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_S_4 : component is "O";
component OBUFT_S_6
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_S_6 : component is "O";
component OBUFT_S_8
 port (
   O : out std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of OBUFT_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_S_8 : component is "O";
component OBUF_AGP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_AGP : component is true;
component OBUF_CTT
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_CTT : component is true;
component OBUF_F_12
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_12 : component is true;
component OBUF_F_16
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_16 : component is true;
component OBUF_F_2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_2 : component is true;
component OBUF_F_24
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_24 : component is true;
component OBUF_F_4
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_4 : component is true;
component OBUF_F_6
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_6 : component is true;
component OBUF_F_8
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_F_8 : component is true;
component OBUF_GTL
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_GTL : component is true;
component OBUF_GTLP
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_GTLP : component is true;
component OBUF_HSTL_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_HSTL_I : component is true;
component OBUF_HSTL_III
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_HSTL_III : component is true;
component OBUF_HSTL_IV
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_HSTL_IV : component is true;
component OBUF_LVCMOS2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_LVCMOS2 : component is true;
component OBUF_PCI33_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_PCI33_3 : component is true;
component OBUF_PCI33_5
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_PCI33_5 : component is true;
component OBUF_PCI66_3
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_PCI66_3 : component is true;
component OBUF_SSTL2_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_SSTL2_I : component is true;
component OBUF_SSTL2_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_SSTL2_II : component is true;
component OBUF_SSTL3_I
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_SSTL3_I : component is true;
component OBUF_SSTL3_II
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_SSTL3_II : component is true;
component OBUF_S_12
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_12 : component is true;
component OBUF_S_16
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_16 : component is true;
component OBUF_S_2
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_2 : component is true;
component OBUF_S_24
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_24 : component is true;
component OBUF_S_4
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_4 : component is true;
component OBUF_S_6
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_6 : component is true;
component OBUF_S_8
 port (
   O : out std_logic;
   I : in std_logic
 );
end component;
attribute syn_black_box of OBUF_S_8 : component is true;
component PULLDOWN
 port (
   O : out std_logic
 );
end component;
attribute syn_black_box of PULLDOWN : component is true;
attribute syn_noprune of PULLDOWN: component is true;
component PULLUP
 port (
   O : out std_logic
 );
end component;
attribute syn_black_box of PULLUP : component is true;
attribute syn_noprune of PULLUP: component is true;
component RAM16X1D
  generic (INIT : bit_vector := X"0000");
 port (
   DPO : out std_logic;
   SPO : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   D : in std_logic;
   DPRA0 : in std_logic;
   DPRA1 : in std_logic;
   DPRA2 : in std_logic;
   DPRA3 : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM16X1D : component is true;
component RAM16X1D_1
  generic (INIT : bit_vector := X"0000");
 port (
   DPO : out std_logic;
   SPO : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   D : in std_logic;
   DPRA0 : in std_logic;
   DPRA1 : in std_logic;
   DPRA2 : in std_logic;
   DPRA3 : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM16X1D_1 : component is true;
component RAM16X1S
  generic (INIT : bit_vector := X"0000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   D : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM16X1S : component is true;
component RAM16X1S_1
  generic (INIT : bit_vector := X"0000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   D : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM16X1S_1 : component is true;
component RAM32X1S
  generic (INIT : bit_vector := X"00000000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   A4 : in std_logic;
   D : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM32X1S : component is true;
component RAM32X1S_1
  generic (INIT : bit_vector := X"00000000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   A4 : in std_logic;
   D : in std_logic;
   WCLK : in std_logic;
   WE : in std_logic
 );
end component;
attribute syn_black_box of RAM32X1S_1 : component is true;
component ROM16X1
  generic (INIT : bit_vector := X"0000");
  port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic
 );
end component;
attribute syn_black_box of ROM16X1 : component is true;
attribute syn_resources of ROM16X1 : component is "luts=1";
component ROM32X1
  generic (INIT : bit_vector := X"00000000");
 port (
   O : out std_logic;
   A0 : in std_logic;
   A1 : in std_logic;
   A2 : in std_logic;
   A3 : in std_logic;
   A4 : in std_logic
 );
end component;
attribute syn_black_box of ROM32X1 : component is true;
attribute syn_resources of ROM32X1 : component is "luts=2";
component RAMB4_S1
 port (
   DO : out std_logic_vector (0 downto 0);
   ADDR : in std_logic_vector (11 downto 0);
   DI : in std_logic_vector (0 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S1 : component is true;
component RAMB4_S16
 port (
   DO : out std_logic_vector (15 downto 0);
   ADDR : in std_logic_vector (7 downto 0);
   DI : in std_logic_vector (15 downto 0);
   EN : in std_logic;
   CLK : in std_logic;
   WE : in std_logic;
   RST : in std_logic
 );
end component;
attribute syn_black_box of RAMB4_S16 : component is true;
component RAMB4_S16_S16
 port (
   DOA : out std_logic_vector (15 downto 0);
   DOB : out std_logic_vector (15 downto 0);
   ADDRA : in std_logic_vector (7 downto 0);
   DIA : in std_logic_vector (15 downto 0);
   ENA : in std_logic;
   CLKA : in std_logic;
   WEA : in std_logic;
   RSTA : in std_logic;
   ADDRB : in std_logic_vector (7 downto 0);
   DIB : in std_logic_vector (15 downto 0);