mult18x18s_instanciate.vhd

学习Xilinx公司开发软件ISE的基础资料

-------------------------------------------------------------------------------
--    Virtex-II Registered Block Multiplier instanciation using Synplify     --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT18X18 cells from behavioral 
--   multiplier descriptions.
--
-- The multiplier resources: (See Virtex-II Handbook for more details)
--     - Logic (CLB resources)
--     - Block multipliers
--          - asynchronous (Primitive: MULT18X18)
--          - synchronous  (Primitive: MULT18X18S)
--              . clock enable
--              . synchronous reset
--          - up to 17x17 unsigned multiplication per cell
--          - up to 18x18 signed multiplication per cell (two's complement)
--          - two small multipliers fit into a single cell (instanciation only)
--
-- NOTES:
--     - Mapping multipliers into MULT18X18 cells (Synplify default)
--          - signed/unsigned 3x3 and wider multiplication support
--          - wider multiplier descriptions than acceptable range by a single
--            cell are automatically decomposed into different cells.
--     - Mapping multipliers into MULT18X18S cells
--          - no support yet for registered MULT18X18S (target release 7.1)
--          - enable the global optimization switch : "Pipelining"
--          - or apply the "syn_pipeline" attribute to the set of registers 
--             on the output of the multiplier
--     - Mapping multipliers into logic
--          - no particular constraints (often slower than block multiplier
--             implementation)
-- Log file message: (Resource Usage Report section)
--          MULT18X18S      1 use
-------------------------------------------------------------------------------
-- Example: Instanciation of a registered outputs block multiplier (MULT18X18S)
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity mult18x18s_instanciate is
  generic ( A_WIDTH : integer := 16;
            B_WIDTH : integer := 16);
  port ( clk : in std_logic;
         ce  : in std_logic;
         a   : in  std_logic_vector(A_WIDTH-1 downto 0);
         b   : in  std_logic_vector(B_WIDTH-1 downto 0);
         p   : out std_logic_vector(A_WIDTH + B_WIDTH -1 downto 0) );
end entity mult18x18s_instanciate;

architecture behavioral of mult18x18s_instanciate is

  signal a_extended, b_extended : std_logic_vector (17 downto 0);
  signal p_bmult_width : std_logic_vector (35 downto 0);
 
  component MULT18X18S
    port ( P  : out std_logic_vector(35 downto 0);
           A  : in std_logic_vector(17 downto 0);
           B  : in std_logic_vector(17 downto 0);
           C  : in std_logic;
           CE : in std_logic;
           R  : in std_logic );
  end component;

begin
  -- sign extention due to cell wider than desired multiplier
  --   i.e. 16 by 16 signed multiplication, cell is 18 by 18
  a_extended <= a(a'high)& a(a'high) & a;
  b_extended <= b(b'high)& b(b'high) & b;
  p          <= p_bmult_width(31 downto 0);

  U0: MULT18X18S 
    port map ( P  => p_bmult_width,
               A  => a_extended,
               B  => b_extended,
               C  => clk,
               CE => ce,
               R  => '0' );

end architecture behavioral;