mult18x18s.vhd

学习Xilinx公司开发软件ISE的基础资料

-------------------------------------------------------------------------------
--      Virtex-II Registered Block Multiplier inference using Synplify       --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT18X18 cells from behavioral 
--   multiplier descriptions.
--
-- The multiplier resources: (See Virtex-II Handbook for more details)
--     - Logic (CLB resources)
--     - Block multipliers
--          - asynchronous (Primitive: MULT18X18)
--          - synchronous  (Primitive: MULT18X18S)
--              . clock enable
--              . synchronous reset
--          - up to 17x17 unsigned multiplication per cell
--          - up to 18x18 signed multiplication per cell (two's complement)
--          - two small multipliers fit into a single cell (instanciation only)
--
-- NOTES:
--     - Mapping multipliers into MULT18X18 cells (Synplify default)
--          - signed/unsigned 3x3 and wider multiplication support
--          - wider multiplier descriptions than acceptable range by a single
--            cell are automatically decomposed into different cells.
--     - Mapping multipliers into MULT18X18S cells
--          - no support yet for registered MULT18X18S (target release 7.1)
--          - enable the global optimization switch : "Pipelining"
--          - or apply the "syn_pipeline" attribute to the set of registers 
--             on the output of the multiplier
--     - Mapping multipliers into logic
--          - no particular constraints (often slower than block multiplier
--             implementation)
-- Log file message: (Resource Usage Report section)
--          MULT18X18S      1 use
-----------------------------------------------------------------------------
-- Example: Signed 16 x 16 multiplier with registered outputs
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;   --signed arithmetics library
--use ieee.std_logic_unsigned.all; --unsigned arithmetics library


entity mult18x18s is
  generic ( A_WIDTH : integer := 32;
            B_WIDTH : integer := 32);
  port ( clk : in std_logic;
         ce  : in std_logic;
         a   : in  std_logic_vector(A_WIDTH-1 downto 0);
         b   : in  std_logic_vector(B_WIDTH-1 downto 0);
         p   : out std_logic_vector(A_WIDTH + B_WIDTH -1 downto 0)
         );
  attribute syn_pipeline : boolean;
  attribute syn_pipeline of p : signal is true;
  -- value: "false" disable pipelining (default)
  -- value: "true" enable pipelining
end entity mult18x18s;

architecture behavioral of mult18x18s is

  signal p_temp : std_logic_vector(p'range);

  attribute syn_multstyle : string;
--  attribute syn_multstyle of p_temp : signal is "logic";
  -- value: "block_mult" force MULT18X18 Virtex-II block multipliers (default)
  -- value: "logic"      disable multiplier mapping to MULT18X18 cells

begin
  process (clk)
  begin
    if rising_edge(clk) then
       if ce = '1' then 
         p <= p_temp;
       end if;
    end if;
  end process;

  p_temp <= a * b;

end architecture behavioral;