srl_static.vhd

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-------------------------------------------------------------------------------
--               Static Shift Register inference using Synplify              --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II Shift-Register cells from different 
--   behavioral descriptions.
--
-- Shift registers implementations: (See Handbook for more details)
--   - Flip-flops
--   - LUTs 
--      - Any LUT can be configured as a 16-bit shift register. (SRL16)
--      - Shift-in operation is synchronous to a positive clock edge (SRL16)
--          or a negative clock edge (SRL16_1).
--      - Output can be static or dynamically selectable.
--      - A dedicated output allows to cascade any number of 16-bit shift 
--          register (SRLC16).
--      - Clock enable, prevent or enable shift operations. (SRL16E)
--      - To improve shift register's clock to out performance, the last stage
--          can be implemented in register.
--
-- NOTES:
--   - Synplify maps to all the above mentionned cells by default as long as:
--      The description represents a set of two or more registers that can be
--      shifted left or right.
--      The contents of only one register can be seen at a time, based on
--      the read address.
--      - Wider shift register descriptions are automatically decomposed into
--          cascaded cells:
--            . SRL16 for static shift register
--            . SRLC16 for dynamic shift register
--
-- ATTRIBUTES:
--   - To prevent automatic inference to shift registers, set the 
--       "syn_srlstyle" attribute to "registers". 
-- Log file message:
--   - Resource Usage Report section (SRL primitives)
--       SRL16          2 uses
-------------------------------------------------------------------------------
-- Example: "valid_in" is delayed  by "SRL_DEPTH" clock cycles
--     (Static Shift Register)
-----------------------------------------------------------------------------*/

library ieee;
use ieee.std_logic_1164.all;

entity srl_static is
  generic ( SRL_DEPTH : integer := 32); -- # clock delays
  port ( clk       : in  std_logic;
         valid_in  : in  std_logic;
         valid_out : out std_logic
       );
end srl_static;

architecture behavioral of srl_static is
  type   srl_datatype is array (SRL_DEPTH-1 downto 0) of std_logic;
  signal lshift_reg : srl_datatype;

  attribute syn_srlstyle : string;
  attribute syn_srlstyle of lshift_reg : signal is "select_srl";
  -- "select_srl"      forces shift register mapping to SRL16 primitives (default)
  -- "registers"       forces shift register mapping to registers 
  -- "noextractff_srl" forces shift register mapping to SRL16 primitives without the timing optimizing output flip-flops

begin
  process (clk)
  begin
    if rising_edge(clk) then
      lshift_reg <= lshift_reg(SRL_DEPTH-2 downto 0) & valid_in;
    end if;
  end process;

  valid_out <= lshift_reg(SRL_DEPTH-1);

end behavioral;