ram_single_port_128x8.plg

来自「学习Xilinx公司开发软件ISE的基础资料」· PLG 代码 · 共 13 行

@P:  Worst Slack : 995.748
@P:  ram_single_port_128x8|clk - Estimated Frequency : 235.2 MHz
@P:  ram_single_port_128x8|clk - Requested Frequency : 1.0 MHz
@P:  ram_single_port_128x8|clk - Estimated Period : 4.252
@P:  ram_single_port_128x8|clk - Requested Period : 1000.000
@P:  ram_single_port_128x8|clk - Slack : 995.748
@P: ram_single_port_128x8 Part : xc2v40cs144-5
@P: ram_single_port_128x8 I/O primitives : 24
@P: ram_single_port_128x8 I/O Register bits : 8
@P: ram_single_port_128x8 Register bits (Non I/O) : 0 (0%)
@P: ram_single_port_128x8 Single Port Rams (RAM128X1S) : 8
@P: ram_single_port_128x8 Total Luts : 64 (12%)