bram_single_128x8_no_change.v

来自「学习Xilinx公司开发软件ISE的基础资料」· Verilog 代码 · 共 66 行

/*-----------------------------------------------------------------------------
--           Single port RAM inference using Synplify                        --
--             (BlockRAM in NO CHANGE mode example)                          --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify can infer a variety RAMs from HDL source code and generate single
--   or dual port RAMs using the distributed or Block RAM resources.
--
-- RAM resources: (See Virtex-II Handbook for details)
--   - Distributed RAM
--      - Single or dual port
--      - Synchronous write and synchronous or asynchronous read
--      - Positive or negative edge clock
--   - BlockRAM
--      - Single or dual port
--      - Synchronous read and write
--      - 18 kbits blocks
--      - Different modes to help manage possible read/write conflict
--
-- INFERENCE LIMITATIONS:
--   - Mapping RAM into Distributed RAM
--      - Synplify default
--   - Mapping RAM to BlockRAM
--      Behavioral description must be a one-to-one correspondence with
--        the following BlockRAM signals:
--         - read and write clocks
--         - read and write addresses
--         - write enable
-- Log file message:
--   - Synplicity Xilinx Technology Mapper section
--      @N Recognized Xilinx Block SelectRAM+
--        RAM mem[7:0] (SINGLEPORT) RAM style NO_CHANGE
--        en = NoName(n/a), rst = NoName(n/a), we = we(pos), clock = clk(pos)
--   - Resource Usage Report section
--      RAMB16_S36      1 use
-------------------------------------------------------------------------------
-- Example: Single port BlockRAM 128x8 in NO CHANGE mode
-----------------------------------------------------------------------------*/

module bram_single_128x8_no_change (di, addr, we, clk, do);
  parameter data_width = 8, addr_width = 7; 

  input  [data_width-1 : 0] di; 
  input  [addr_width-1 : 0] addr; 
  input                     we;
  input                     clk;
  output [data_width-1 : 0] do; 

  reg    [data_width-1 : 0] do; 
  reg    [data_width-1 : 0] mem [(1 << addr_width)-1 : 0] /* synthesis syn_ramstyle = "block_ram" */ ;
  // value: "select_ram"  forces Distributed RAM implementation (default)
  // value: "registers"   forces Registers   RAM implementation
  // value: "block_ram"   forces BlockRAM    RAM implementation
  // value: "no_rw_check" forces BlockRAM    RAM implementation with no
  //                                  read/write address conflict checking

  always @(posedge clk) 
    if (we == 1'b1)
      mem[addr] = di; 
    else 
      do = mem[addr]; 

endmodule