mult_and.v

来自「学习Xilinx公司开发软件ISE的基础资料」· Verilog 代码 · 共 45 行

/*-----------------------------------------------------------------------------
--          Virtex-II MULT_AND cell inference using Synplify                 --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify automatically infers Virtex-II MULT_AND cells for certain 
--     arithmetics behavioral descriptions.
--
-- MULT_AND resources: (See Virtex-II Handbook for more details)
--     - One MULT_AND gate is associate with each LUT and drives an input to 
--       the carry chain, speeding up implementation of multipliers and other
--       arithmetics operations.
--
-- STATUS:
--     - Synplify automaticaly infers MULT_AND cells for distributed 
--       multipliers descriptions
--     - Other arithmetic functions that could take advantage of the MULT_AND
--       will be implemented in the future (target release 7.1)
-------------------------------------------------------------------------------
-- Example: Signed 16 x 16 multiplier with registered outputs
-----------------------------------------------------------------------------*/

module mult18x18 (clk, ce, a, b, p);
  input         clk;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;

  reg [31:0] p;
  wire   [31:0] p_temp /* synthesis syn_multstyle = "logic" */ ;
  // value: "block_mult" force MULT18X18 Virtex-II block multipliers (default)
  // value: "logic"      disable multiplier mapping to MULT18X18 cells

  always @(posedge clk)
  begin
    if (ce == 1'b1)
      p <= p_temp;
  end

  assign p_temp = a * b;

endmodule