bufgce_instanciate.v

来自「学习Xilinx公司开发软件ISE的基础资料」· Verilog 代码 · 共 52 行

/*-----------------------------------------------------------------------------
--                 BUFGCE instanciation using Synplify                       --
-------------------------------------------------------------------------------
--
-- GENERAL:
--   Synplify does not infer BUFGCE: Instanciation is required.
--
-- The BUFGCE resources: (See Virtex-II Handbook for more details)
--   - BUFGCE is a multiplexed global clock buffer with a single gated input.
--     Its output is constant when clock-enable is inactive. When 
--     clock-enable is active, the input is transferred to the output. 
--   - BUFGCE  : output is low  when clock-enable is inactive
--   - BUFGCE_1: output is high when clock-enable is inactive
--   - Application: reducing power and routing
--
-- NOTES:
--   - Inference scheduled for release 7.2
--   - Instanciation: If the input of the BUFGCE is an external signal than the
--      "xc_padtype" attribute is recommended. By default Synplify infers a 
--      IBUF instead of a IBUFG for that clock pad signal resulting in a slower
--      design (attribute no longuer needed in release 7.1)
-------------------------------------------------------------------------------
-- Example: BUFGCE instanciation
-----------------------------------------------------------------------------*/

module bufgce_instanciate (clk_pad, ce, a, b, p);
  input         clk_pad /* synthesis xc_padtype = "IBUFG" */;
  input         ce;
  input  [15:0] a;
  input  [15:0] b;
  output [31:0] p;

  reg    [31:0] p;

// BUFGCE instanciation
  BUFGCE U1 ( .O(clk),
              .CE(ce),
              .I(clk_pad) );

// Equivalent BUFGCE behavioral description (Not available yet for inference)
//  clk <= clk_pad and not ce;           -- Not available yet for inference 
//  clk <= clk_pad when ce='1' else '0'; -- Not available yet for inference

// other code
  always @(posedge clk)
  begin
       p <= a * b;
  end

endmodule