fdq.stx

来自「学习Xilinx公司开发软件ISE的基础资料」· STX 代码 · 共 24 行

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "fdq.sprj"
Compiling include file "fdq.vf"
Module <fdq> compiled
Compiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation
Analysis of file <fdq.sprj> succeeded.

CPU : 0.74 / 1.13 s | Elapsed : 0.00 / 1.00 s
 
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Total memory usage is 52080 kilobytes