📄 fdq.stx
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Release 5.1i - xst F.23Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 1.00 s --> =========================================================================* HDL Compilation *=========================================================================Compiling source file "fdq.sprj"Compiling include file "fdq.vf"Module <fdq> compiledCompiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"No errors in compilationAnalysis of file <fdq.sprj> succeeded.CPU : 0.74 / 1.13 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 52080 kilobytes
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