📄 sanjiaobo.edf
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(port CD
(direction INPUT))
(port D0
(direction INPUT))
(port G
(direction INPUT))
(port PD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FDE1E
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CD
(direction INPUT))
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port EN
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FDE1
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CD
(direction INPUT))
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FDC1E
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port EN
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FDC1
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FD21E
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CD
(direction INPUT))
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port EN
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FD11E
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port D0
(direction INPUT))
(port EN
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FJK71
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CD
(direction INPUT))
(port CLK
(direction INPUT))
(port J0
(direction INPUT))
(port K0
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FJK61
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port J0
(direction INPUT))
(port K0
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FTI21
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port T0
(direction INPUT))
(port CLK
(direction INPUT))
(port CD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FTI31
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port T0
(direction INPUT))
(port CLK
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
(cell FTI41
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port T0
(direction INPUT))
(port CLK
(direction INPUT))
(port CD
(direction INPUT))
(port SD
(direction INPUT))
(port Q0
(direction OUTPUT)))))
)
(library SANJIAOBO
(ediflevel 0)
(technology (numberDefinition))
(cell SANJIAOBO
(cellType GENERIC)
(view NetList
(viewType NETLIST)
(interface
(port CONTROL
(direction INPUT))
(port Q5
(direction OUTPUT))
(port Q4
(direction OUTPUT))
(port Q3
(direction OUTPUT))
(port Q2
(direction OUTPUT))
(port Q1
(direction OUTPUT))
(port Q0
(direction OUTPUT))
(port CP
(direction INPUT)))
(contents
(instance IN_CONTROL_U1
(viewRef NetList
(cellRef IB11
(libraryRef plsi))))
(instance OUT_Q5_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance OUT_Q4_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance OUT_Q3_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance OUT_Q2_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance OUT_Q1_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance OUT_Q0_U1
(viewRef NetList
(cellRef OB11
(libraryRef plsi))))
(instance IN_CP_U1
(viewRef NetList
(cellRef IB11
(libraryRef plsi))))
(instance FF_Q5_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance FF_Q4_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance FF_Q3_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance FF_Q2_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance FF_Q1_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance FF_Q0_U1
(viewRef NetList
(cellRef FD11
(libraryRef plsi))))
(instance GATE_Q5_D_REG_U1
(viewRef NetList
(cellRef AND4
(libraryRef plsi))))
(instance GATE_Q4_D_REG_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_Q3_D_REG_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_Q2_D_REG_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_Q1_D_REG_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_Q0_D_REG_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__0_I_3
(viewRef NetList
(cellRef NAND2
(libraryRef plsi))))
(instance GATE_T__0_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__0_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__1_I_3
(viewRef NetList
(cellRef NAND2
(libraryRef plsi))))
(instance GATE_T__1_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__1_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__2_I_3
(viewRef NetList
(cellRef NAND2
(libraryRef plsi))))
(instance GATE_T__2_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__2_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__3_I_3
(viewRef NetList
(cellRef NAND2
(libraryRef plsi))))
(instance GATE_T__3_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__3_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__4_I_3
(viewRef NetList
(cellRef NAND2
(libraryRef plsi))))
(instance GATE_T__4_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__4_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__5_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__5_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__5_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__6_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__6_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__7_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__7_U3
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__7_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__8_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__8_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__9_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__9_U3
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__9_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__10_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__10_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__11_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__11_U3
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__11_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__12_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__12_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__13_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__13_U3
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__13_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__14_I_4
(viewRef NetList
(cellRef AND3
(libraryRef plsi))))
(instance GATE_T__14_I_2
(viewRef NetList
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