sanjiaobo.edf
来自「这是一个用abel语言编写的三角波发生器」· EDF 代码 · 共 1,741 行 · 第 1/4 页
EDF
1,741 行
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__15_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__15_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__15_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__16_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__16_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__16_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__17_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__17_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__17_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__18_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__18_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__18_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__19_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__19_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__19_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__20_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__20_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__20_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__21_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__21_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__21_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__22_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__22_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__22_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__23_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__23_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__23_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__24_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__24_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__24_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__25_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__25_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__25_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__26_I_2
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__26_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__26_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(instance GATE_T__27_I_1
(viewRef NetList
(cellRef INV
(libraryRef plsi))))
(instance GATE_T__27_U1
(viewRef NetList
(cellRef AND2
(libraryRef plsi))))
(net CONTROL
(joined
(portRef CONTROL)
(portRef XI0
(instanceRef IN_CONTROL_U1))))
(net CONTROL_PIN_BLIF
(joined
(portRef Z0
(instanceRef IN_CONTROL_U1))
(portRef A0
(instanceRef GATE_Q5_D_REG_U1))
(portRef A0
(instanceRef GATE_T__5_I_2))
(portRef A1
(instanceRef GATE_T__6_U1))
(portRef A0
(instanceRef GATE_T__7_I_2))
(portRef A1
(instanceRef GATE_T__8_I_4))
(portRef A0
(instanceRef GATE_T__9_I_2))
(portRef A1
(instanceRef GATE_T__10_I_4))
(portRef A0
(instanceRef GATE_T__11_I_2))
(portRef A1
(instanceRef GATE_T__12_I_4))
(portRef A0
(instanceRef GATE_T__13_I_2))
(portRef A1
(instanceRef GATE_T__14_I_4))))
(net Q5
(joined
(portRef Q5)
(portRef XO0
(instanceRef OUT_Q5_U1))))
(net Q5_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q5_U1))
(portRef Q0
(instanceRef FF_Q5_U1))
(portRef A0
(instanceRef GATE_T__5_I_1))
(portRef A2
(instanceRef GATE_T__13_I_4))
(portRef A0
(instanceRef GATE_T__14_I_2))
(portRef A0
(instanceRef GATE_T__18_I_1))
(portRef A0
(instanceRef GATE_T__20_I_1))
(portRef A0
(instanceRef GATE_T__22_I_1))
(portRef A0
(instanceRef GATE_T__27_I_1))))
(net Q4
(joined
(portRef Q4)
(portRef XO0
(instanceRef OUT_Q4_U1))))
(net Q4_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q4_U1))
(portRef Q0
(instanceRef FF_Q4_U1))
(portRef A2
(instanceRef GATE_T__11_I_4))
(portRef A0
(instanceRef GATE_T__12_I_2))
(portRef A0
(instanceRef GATE_T__16_I_1))
(portRef A0
(instanceRef GATE_T__18_I_2))
(portRef A0
(instanceRef GATE_T__20_I_2))
(portRef A0
(instanceRef GATE_T__24_I_1))
(portRef A1
(instanceRef GATE_T__27_U1))))
(net Q3
(joined
(portRef Q3)
(portRef XO0
(instanceRef OUT_Q3_U1))))
(net Q3_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q3_U1))
(portRef Q0
(instanceRef FF_Q3_U1))
(portRef A2
(instanceRef GATE_T__9_I_4))
(portRef A0
(instanceRef GATE_T__10_I_2))
(portRef A0
(instanceRef GATE_T__13_U3))
(portRef A2
(instanceRef GATE_T__14_I_4))
(portRef A0
(instanceRef GATE_T__16_I_2))
(portRef A0
(instanceRef GATE_T__17_I_1))
(portRef A0
(instanceRef GATE_T__22_I_2))
(portRef A0
(instanceRef GATE_T__26_I_1))))
(net Q2
(joined
(portRef Q2)
(portRef XO0
(instanceRef OUT_Q2_U1))))
(net Q2_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q2_U1))
(portRef Q0
(instanceRef FF_Q2_U1))
(portRef A2
(instanceRef GATE_T__7_I_4))
(portRef A0
(instanceRef GATE_T__8_I_2))
(portRef A0
(instanceRef GATE_T__11_U3))
(portRef A2
(instanceRef GATE_T__12_I_4))
(portRef A0
(instanceRef GATE_T__15_I_1))
(portRef A0
(instanceRef GATE_T__19_I_1))
(portRef A0
(instanceRef GATE_T__24_I_2))
(portRef A0
(instanceRef GATE_T__26_I_2))))
(net Q1
(joined
(portRef Q1)
(portRef XO0
(instanceRef OUT_Q1_U1))))
(net Q1_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q1_U1))
(portRef Q0
(instanceRef FF_Q1_U1))
(portRef A0
(instanceRef GATE_T__6_I_1))
(portRef A0
(instanceRef GATE_T__9_U3))
(portRef A2
(instanceRef GATE_T__10_I_4))
(portRef A0
(instanceRef GATE_T__17_I_2))
(portRef A0
(instanceRef GATE_T__21_I_1))
(portRef A0
(instanceRef GATE_T__23_I_1))
(portRef A0
(instanceRef GATE_T__25_I_1))))
(net Q0
(joined
(portRef Q0)
(portRef XO0
(instanceRef OUT_Q0_U1))))
(net Q0_Q_BLIF
(joined
(portRef A0
(instanceRef OUT_Q0_U1))
(portRef Q0
(instanceRef FF_Q0_U1))
(portRef A0
(instanceRef GATE_T__7_U3))
(portRef A2
(instanceRef GATE_T__8_I_4))
(portRef A0
(instanceRef GATE_T__15_I_2))
(portRef A0
(instanceRef GATE_T__19_I_2))
(portRef A0
(instanceRef GATE_T__21_I_2))
(portRef A0
(instanceRef GATE_T__23_I_2))
(portRef A0
(instanceRef GATE_T__25_I_2))))
(net CP
(joined
(portRef CP)
(portRef XI0
(instanceRef IN_CP_U1))))
(net CP_PIN_BLIF
(joined
(portRef Z0
(instanceRef IN_CP_U1))
(portRef CLK
(instanceRef FF_Q5_U1))
(portRef CLK
(instanceRef FF_Q4_U1))
(portRef CLK
(instanceRef FF_Q3_U1))
(portRef CLK
(instanceRef FF_Q2_U1))
(portRef CLK
(instanceRef FF_Q1_U1))
(portRef CLK
(instanceRef FF_Q0_U1))))
(net Q5_D_REG
(joined
(portRef D0
(instanceRef FF_Q5_U1))
(portRef Z0
(instanceRef GATE_Q5_D_REG_U1))))
(net Q4_D_REG
(joined
(portRef D0
(instanceRef FF_Q4_U1))
(portRef Z0
(instanceRef GATE_Q4_D_REG_I_4))))
(net Q3_D_REG
(joined
(portRef D0
(instanceRef FF_Q3_U1))
(portRef Z0
(instanceRef GATE_Q3_D_REG_I_4))))
(net Q2_D_REG
(joined
(portRef D0
(instanceRef FF_Q2_U1))
(portRef Z0
(instanceRef GATE_Q2_D_REG_I_4))))
(net Q1_D_REG
(joined
(portRef D0
(instanceRef FF_Q1_U1))
(portRef Z0
(instanceRef GATE_Q1_D_REG_I_4))))
(net Q0_D_REG
(joined
(portRef D0
(instanceRef FF_Q0_U1))
(portRef Z0
(instanceRef GATE_Q0_D_REG_I_4))))
(net T__0
(joined
(portRef A1
(instanceRef GATE_Q4_D_REG_I_4))
(portRef ZN0
(instanceRef GATE_T__0_I_3))))
(net T__1
(joined
(portRef A1
(instanceRef GATE_Q3_D_REG_I_4))
(portRef ZN0
(instanceRef GATE_T__1_I_3))))
(net T__2
(joined
(portRef A1
(instanceRef GATE_Q2_D_REG_I_4))
(portRef ZN0
(instanceRef GATE_T__2_I_3))))
(net T__3
(joined
(portRef A1
(instanceRef GATE_Q1_D_REG_I_4))
(portRef ZN0
(instanceRef GATE_T__3_I_3))))
(net T__4
(joined
(portRef A1
(instanceRef GATE_Q0_D_REG_I_4))
(portRef ZN0
(instanceRef GATE_T__4_I_3))))
(net T__5
(joined
(portRef A0
(instanceRef GATE_T__4_I_1))
(portRef Z0
(instanceRef GATE_T__5_U1))))
(net T__6
(joined
(portRef A0
(instanceRef GATE_T__4_I_2))
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