📄 light.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 14 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] register RGB:U2\|CURRENT_STATE\[7\] 65.79 MHz 15.2 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 65.79 MHz between source register \"CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]\" and destination register \"RGB:U2\|CURRENT_STATE\[7\]\" (period= 15.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.100 ns + Longest register register " "Info: + Longest register to register delay is 14.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 1 REG LC6_D31 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_D31; Fanout = 8; REG Node = 'CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 2.700 ns RGB:U2\|Equal1~48 2 COMB LC7_D33 2 " "Info: 2: + IC(1.000 ns) + CELL(1.700 ns) = 2.700 ns; Loc. = LC7_D33; Fanout = 2; COMB Node = 'RGB:U2\|Equal1~48'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] RGB:U2|Equal1~48 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 4.600 ns RGB:U2\|Equal6~34 3 COMB LC1_D33 2 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 4.600 ns; Loc. = LC1_D33; Fanout = 2; COMB Node = 'RGB:U2\|Equal6~34'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { RGB:U2|Equal1~48 RGB:U2|Equal6~34 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 7.200 ns RGB:U2\|Mux0~235 4 COMB LC5_D34 3 " "Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.200 ns; Loc. = LC5_D34; Fanout = 3; COMB Node = 'RGB:U2\|Mux0~235'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { RGB:U2|Equal6~34 RGB:U2|Mux0~235 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 9.600 ns RGB:U2\|Mux0~236 5 COMB LC2_D36 1 " "Info: 5: + IC(1.000 ns) + CELL(1.400 ns) = 9.600 ns; Loc. = LC2_D36; Fanout = 1; COMB Node = 'RGB:U2\|Mux0~236'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { RGB:U2|Mux0~235 RGB:U2|Mux0~236 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 11.300 ns RGB:U2\|Mux0~237 6 COMB LC5_D36 1 " "Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 11.300 ns; Loc. = LC5_D36; Fanout = 1; COMB Node = 'RGB:U2\|Mux0~237'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { RGB:U2|Mux0~236 RGB:U2|Mux0~237 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 13.000 ns RGB:U2\|Mux0~238 7 COMB LC7_D36 1 " "Info: 7: + IC(0.300 ns) + CELL(1.400 ns) = 13.000 ns; Loc. = LC7_D36; Fanout = 1; COMB Node = 'RGB:U2\|Mux0~238'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.700 ns" { RGB:U2|Mux0~237 RGB:U2|Mux0~238 } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.800 ns) 14.100 ns RGB:U2\|CURRENT_STATE\[7\] 8 REG LC1_D36 12 " "Info: 8: + IC(0.300 ns) + CELL(0.800 ns) = 14.100 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2\|CURRENT_STATE\[7\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.100 ns" { RGB:U2|Mux0~238 RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.900 ns ( 70.21 % ) " "Info: Total cell delay = 9.900 ns ( 70.21 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 29.79 % ) " "Info: Total interconnect delay = 4.200 ns ( 29.79 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.100 ns" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] RGB:U2|Equal1~48 RGB:U2|Equal6~34 RGB:U2|Mux0~235 RGB:U2|Mux0~236 RGB:U2|Mux0~237 RGB:U2|Mux0~238 RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "14.100 ns" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] RGB:U2|Equal1~48 RGB:U2|Equal6~34 RGB:U2|Mux0~235 RGB:U2|Mux0~236 RGB:U2|Mux0~237 RGB:U2|Mux0~238 RGB:U2|CURRENT_STATE[7] } { 0.000ns 1.000ns 0.300ns 1.000ns 1.000ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.600ns 1.600ns 1.400ns 1.400ns 1.400ns 0.800ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns RGB:U2\|CURRENT_STATE\[7\] 2 REG LC1_D36 12 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2\|CURRENT_STATE\[7\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out RGB:U2|CURRENT_STATE[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\] 2 REG LC6_D31 8 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_D31; Fanout = 8; REG Node = 'CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[4\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out RGB:U2|CURRENT_STATE[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.100 ns" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] RGB:U2|Equal1~48 RGB:U2|Equal6~34 RGB:U2|Mux0~235 RGB:U2|Mux0~236 RGB:U2|Mux0~237 RGB:U2|Mux0~238 RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "14.100 ns" { CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] RGB:U2|Equal1~48 RGB:U2|Equal6~34 RGB:U2|Mux0~235 RGB:U2|Mux0~236 RGB:U2|Mux0~237 RGB:U2|Mux0~238 RGB:U2|CURRENT_STATE[7] } { 0.000ns 1.000ns 0.300ns 1.000ns 1.000ns 0.300ns 0.300ns 0.300ns } { 0.000ns 1.700ns 1.600ns 1.600ns 1.400ns 1.400ns 1.400ns 0.800ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out RGB:U2|CURRENT_STATE[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK light\[7\] RGB:U2\|CURRENT_STATE\[7\] 11.600 ns register " "Info: tco from clock \"CLK\" to destination pin \"light\[7\]\" through register \"RGB:U2\|CURRENT_STATE\[7\]\" is 11.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns RGB:U2\|CURRENT_STATE\[7\] 2 REG LC1_D36 12 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2\|CURRENT_STATE\[7\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out RGB:U2|CURRENT_STATE[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register pin " "Info: + Longest register to pin delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RGB:U2\|CURRENT_STATE\[7\] 1 REG LC1_D36 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2\|CURRENT_STATE\[7\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(6.300 ns) 8.700 ns light\[7\] 2 PIN PIN_92 0 " "Info: 2: + IC(2.400 ns) + CELL(6.300 ns) = 8.700 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'light\[7\]'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { RGB:U2|CURRENT_STATE[7] light[7] } "NODE_NAME" } } { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 72.41 % ) " "Info: Total cell delay = 6.300 ns ( 72.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 27.59 % ) " "Info: Total interconnect delay = 2.400 ns ( 27.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { RGB:U2|CURRENT_STATE[7] light[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { RGB:U2|CURRENT_STATE[7] light[7] } { 0.000ns 2.400ns } { 0.000ns 6.300ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK RGB:U2|CURRENT_STATE[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out RGB:U2|CURRENT_STATE[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { RGB:U2|CURRENT_STATE[7] light[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { RGB:U2|CURRENT_STATE[7] light[7] } { 0.000ns 2.400ns } { 0.000ns 6.300ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 16 18:32:00 2008 " "Info: Processing ended: Mon Jun 16 18:32:00 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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