light.map.qmsg

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 -

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 16 18:31:48 2008 " "Info: Processing started: Mon Jun 16 18:31:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LIGHT -c LIGHT " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LIGHT -c LIGHT" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNT109.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNT109.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT109-behav " "Info: Found design unit 1: CNT109-behav" {  } { { "CNT109.vhd" "" { Text "E:/study/EDA/LIGHT/CNT109.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT109 " "Info: Found entity 1: CNT109" {  } { { "CNT109.vhd" "" { Text "E:/study/EDA/LIGHT/CNT109.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LIGHT.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file LIGHT.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LIGHT-ONE " "Info: Found design unit 1: LIGHT-ONE" {  } { { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LIGHT " "Info: Found entity 1: LIGHT" {  } { { "LIGHT.VHD" "" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RGY.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RGY.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RGB-BEHAV " "Info: Found design unit 1: RGB-BEHAV" {  } { { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RGB " "Info: Found entity 1: RGB" {  } { { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LIGHT " "Info: Elaborating entity \"LIGHT\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT109 CNT109:U1 " "Info: Elaborating entity \"CNT109\" for hierarchy \"CNT109:U1\"" {  } { { "LIGHT.VHD" "U1" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 30 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CQI CNT109.vhd(27) " "Warning (10492): VHDL Process Statement warning at CNT109.vhd(27): signal \"CQI\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "CNT109.vhd" "" { Text "E:/study/EDA/LIGHT/CNT109.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RGB RGB:U2 " "Info: Elaborating entity \"RGB\" for hierarchy \"RGB:U2\"" {  } { { "LIGHT.VHD" "U2" { Text "E:/study/EDA/LIGHT/LIGHT.VHD" 31 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "CNT109:U1\|CQI\[0\]~7 7 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=7) from the following logic: \"CNT109:U1\|CQI\[0\]~7\"" {  } { { "CNT109.vhd" "CQI\[0\]~7" { Text "E:/study/EDA/LIGHT/CNT109.vhd" 20 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CNT109:U1\|lpm_counter:CQI_rtl_0 " "Info: Elaborated megafunction instantiation \"CNT109:U1\|lpm_counter:CQI_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter CNT109:U1\|lpm_counter:CQI_rtl_0 " "Info: Elaborated megafunction instantiation \"CNT109:U1\|lpm_counter:CQI_rtl_0\|alt_counter_f10ke:wysi_counter\", which is child of megafunction instantiation \"CNT109:U1\|lpm_counter:CQI_rtl_0\"" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 417 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CNT109:U1\|lpm_counter:CQI_rtl_0 " "Info: Instantiated megafunction \"CNT109:U1\|lpm_counter:CQI_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Info: Parameter \"LPM_WIDTH\" = \"7\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } } { "RGY.vhd" "" { Text "E:/study/EDA/LIGHT/RGY.vhd" 43 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "68 " "Info: Implemented 68 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 16 18:31:50 2008 " "Info: Processing ended: Mon Jun 16 18:31:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}