light.tan.rpt

--author: Suntion Tang --date: 2008-6-7 -- two warning --modify: By Suntion Tang at 2008-6-14 -

; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; CLK        ; CLK      ; None                        ; None                      ; 1.600 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK        ; CLK      ; None                        ; None                      ; 1.400 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK        ; CLK      ; None                        ; None                      ; 1.200 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK        ; CLK      ; None                        ; None                      ; 1.000 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK        ; CLK      ; None                        ; None                      ; 1.000 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+-------------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From                    ; To       ; From Clock ;
+-------+--------------+------------+-------------------------+----------+------------+
; N/A   ; None         ; 11.600 ns  ; RGB:U2|CURRENT_STATE[7] ; light[7] ; CLK        ;
; N/A   ; None         ; 11.500 ns  ; RGB:U2|CURRENT_STATE[0] ; light[0] ; CLK        ;
; N/A   ; None         ; 10.600 ns  ; RGB:U2|CURRENT_STATE[6] ; light[6] ; CLK        ;
; N/A   ; None         ; 10.600 ns  ; RGB:U2|CURRENT_STATE[5] ; light[5] ; CLK        ;
; N/A   ; None         ; 10.500 ns  ; RGB:U2|CURRENT_STATE[4] ; light[4] ; CLK        ;
; N/A   ; None         ; 10.500 ns  ; RGB:U2|CURRENT_STATE[3] ; light[3] ; CLK        ;
; N/A   ; None         ; 10.400 ns  ; RGB:U2|CURRENT_STATE[2] ; light[2] ; CLK        ;
; N/A   ; None         ; 10.000 ns  ; RGB:U2|CURRENT_STATE[1] ; light[1] ; CLK        ;
+-------+--------------+------------+-------------------------+----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 16 18:32:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LIGHT -c LIGHT
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 65.79 MHz between source register "CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]" and destination register "RGB:U2|CURRENT_STATE[7]" (period= 15.2 ns)
    Info: + Longest register to register delay is 14.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_D31; Fanout = 8; REG Node = 'CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
        Info: 2: + IC(1.000 ns) + CELL(1.700 ns) = 2.700 ns; Loc. = LC7_D33; Fanout = 2; COMB Node = 'RGB:U2|Equal1~48'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 4.600 ns; Loc. = LC1_D33; Fanout = 2; COMB Node = 'RGB:U2|Equal6~34'
        Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 7.200 ns; Loc. = LC5_D34; Fanout = 3; COMB Node = 'RGB:U2|Mux0~235'
        Info: 5: + IC(1.000 ns) + CELL(1.400 ns) = 9.600 ns; Loc. = LC2_D36; Fanout = 1; COMB Node = 'RGB:U2|Mux0~236'
        Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 11.300 ns; Loc. = LC5_D36; Fanout = 1; COMB Node = 'RGB:U2|Mux0~237'
        Info: 7: + IC(0.300 ns) + CELL(1.400 ns) = 13.000 ns; Loc. = LC7_D36; Fanout = 1; COMB Node = 'RGB:U2|Mux0~238'
        Info: 8: + IC(0.300 ns) + CELL(0.800 ns) = 14.100 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2|CURRENT_STATE[7]'
        Info: Total cell delay = 9.900 ns ( 70.21 % )
        Info: Total interconnect delay = 4.200 ns ( 29.79 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_D36; Fanout = 12; REG Node = 'RGB:U2|CURRENT_STATE[7]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_D31; Fanout = 8; REG Node = 'CNT109:U1|lpm_counter:CQI_rtl_0|alt_counter_f10ke:wysi_counter|q[4]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "CLK" to destination pin "light[7]" through register "RGB:U2|CURRENT_STATE[7]" is 11.600 ns
    Info: