div.tan.qmsg

该源码为VHDL语言编写的分频器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 02 21:24:21 2008 " "Info: Processing started: Mon Jun 02 21:24:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off div -c div " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B\[2\] quotient\[3\] 17.600 ns Longest " "Info: Longest tpd from source pin \"B\[2\]\" to destination pin \"quotient\[3\]\" is 17.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns B\[2\] 1 PIN PIN_96 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_96; Fanout = 4; PIN Node = 'B\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { B[2] } "NODE_NAME" } } { "div.vhd" "" { Text "E:/study/EDA/div/div.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.700 ns) 8.000 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 2 COMB LC7_C21 1 " "Info: 2: + IC(2.400 ns) + CELL(0.700 ns) = 8.000 ns; Loc. = LC7_C21; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.100 ns" { B[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 9.400 ns lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[4\] 3 COMB LC8_C21 1 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 9.400 ns; Loc. = LC8_C21; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } { "addcore.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(6.300 ns) 17.600 ns quotient\[3\] 4 PIN PIN_95 0 " "Info: 4: + IC(1.900 ns) + CELL(6.300 ns) = 17.600 ns; Loc. = PIN_95; Fanout = 0; PIN Node = 'quotient\[3\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.200 ns" { lpm_add_sub:Add0|addcore:adder|unreg_res_node[4] quotient[3] } "NODE_NAME" } } { "div.vhd" "" { Text "E:/study/EDA/div/div.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.300 ns ( 75.57 % ) " "Info: Total cell delay = 13.300 ns ( 75.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 24.43 % ) " "Info: Total interconnect delay = 4.300 ns ( 24.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.600 ns" { B[2] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|unreg_res_node[4] quotient[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "17.600 ns" { B[2] B[2]~out lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:Add0|addcore:adder|unreg_res_node[4] quotient[3] } { 0.000ns 0.000ns 2.400ns 0.000ns 1.900ns } { 0.000ns 4.900ns 0.700ns 1.400ns 6.300ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 02 21:24:22 2008 " "Info: Processing ended: Mon Jun 02 21:24:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}