div.fit.summary

该源码为VHDL语言编写的分频器

Fitter Status : Successful - Mon Jun 02 21:24:17 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : div
Top-level Entity Name : div
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Total logic elements : 8 / 1,728 ( < 1 % )
Total pins : 16 / 102 ( 16 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0