div.vhd

该源码为VHDL语言编写的分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY div IS
PORT ( 
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
arithmetical_compliment: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
quotient: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ;
ARCHITECTURE behav OF div IS
BEGIN
process(A,B)
begin
quotient<=A - B;
arithmetical_compliment<=A + B;
end process;
END behav;