selector.vhd

来自「VHDL编写的数字钟」· VHDL 代码 · 共 14 行

ENTITY selector IS
PORT ( a, b, s: IN BIT;
y : OUT BIT );
END ;
ARCHITECTURE one OF selector IS
BEGIN
PROCESS (a,b,s)
BEGIN
IF s = '0' THEN
y <= a ; ELSE
y <= b ;
END IF;
END PROCESS;
END ARCHITECTURE one ;