txxclock.tan.qmsg

来自「VHDL编写的数字钟」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "selector12:inst12\|x " "Warning: Node \"selector12:inst12\|x\" is a latch" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 14 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "selector12:inst12\|y " "Warning: Node \"selector12:inst12\|y\" is a latch" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 15 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "selector12:inst10\|x " "Warning: Node \"selector12:inst10\|x\" is a latch" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 14 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "selector12:inst10\|y " "Warning: Node \"selector12:inst10\|y\" is a latch" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 15 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}