txxclock.map.qmsg

VHDL编写的数字钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 01 17:18:11 2008 " "Info: Processing started: Sun Jun 01 17:18:11 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off txxclock -c txxclock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off txxclock -c txxclock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cmp32B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cmp32B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cmp32B-behav " "Info: Found design unit 1: cmp32B-behav" {  } { { "cmp32B.vhd" "" { Text "E:/study/EDA/myclock/txxclock/cmp32B.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cmp32B " "Info: Found entity 1: cmp32B" {  } { { "cmp32B.vhd" "" { Text "E:/study/EDA/myclock/txxclock/cmp32B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-behav " "Info: Found design unit 1: hour-behav" {  } { { "hour.vhd" "" { Text "E:/study/EDA/myclock/txxclock/hour.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "E:/study/EDA/myclock/txxclock/hour.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "minute.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file minute.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute-behav " "Info: Found design unit 1: minute-behav" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "minute.vhd" "" { Text "E:/study/EDA/myclock/txxclock/minute.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mode.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mode-behav " "Info: Found design unit 1: mode-behav" {  } { { "mode.vhd" "" { Text "E:/study/EDA/myclock/txxclock/mode.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mode " "Info: Found entity 1: mode" {  } { { "mode.vhd" "" { Text "E:/study/EDA/myclock/txxclock/mode.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file second.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-behav " "Info: Found design unit 1: second-behav" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.vhd" "" { Text "E:/study/EDA/myclock/txxclock/second.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "selector.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file selector.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 selector-one " "Info: Found design unit 1: selector-one" {  } { { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 selector " "Info: Found entity 1: selector" {  } { { "selector.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector.vhd" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "selector12.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file selector12.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 selector12-one " "Info: Found design unit 1: selector12-one" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 selector12 " "Info: Found entity 1: selector12" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "selector217.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file selector217.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 selector217-one " "Info: Found design unit 1: selector217-one" {  } { { "selector217.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector217.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 selector217 " "Info: Found entity 1: selector217" {  } { { "selector217.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector217.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "txxclock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file txxclock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 txxclock " "Info: Found entity 1: txxclock" {  } { { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "txxclock " "Info: Elaborating entity \"txxclock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "a selector inst11 " "Warning: Port \"a\" of type selector and instance \"inst11\" is missing source signal" {  } { { "txxclock.bdf" "" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 240 904 1000 336 "inst11" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "selector selector:inst11 " "Info: Elaborating entity \"selector\" for hierarchy \"selector:inst11\"" {  } { { "txxclock.bdf" "inst11" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 240 904 1000 336 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmp32B cmp32B:inst7 " "Info: Elaborating entity \"cmp32B\" for hierarchy \"cmp32B:inst7\"" {  } { { "txxclock.bdf" "inst7" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 120 928 1024 216 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:inst1 " "Info: Elaborating entity \"minute\" for hierarchy \"minute:inst1\"" {  } { { "txxclock.bdf" "inst1" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 112 416 512 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "selector12 selector12:inst10 " "Info: Elaborating entity \"selector12\" for hierarchy \"selector12:inst10\"" {  } { { "txxclock.bdf" "inst10" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 368 184 280 464 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "x selector12.vhd(19) " "Warning (10631): VHDL Process Statement warning at selector12.vhd(19): inferring latch(es) for signal or variable \"x\", which holds its previous value in one or more paths through the process" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 19 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y selector12.vhd(19) " "Warning (10631): VHDL Process Statement warning at selector12.vhd(19): inferring latch(es) for signal or variable \"y\", which holds its previous value in one or more paths through the process" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 19 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "y selector12.vhd(19) " "Info (10041): Verilog HDL or VHDL info at selector12.vhd(19): inferred latch for \"y\"" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "x selector12.vhd(19) " "Info (10041): Verilog HDL or VHDL info at selector12.vhd(19): inferred latch for \"x\"" {  } { { "selector12.vhd" "" { Text "E:/study/EDA/myclock/txxclock/selector12.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mode mode:inst9 " "Info: Elaborating entity \"mode\" for hierarchy \"mode:inst9\"" {  } { { "txxclock.bdf" "inst9" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 392 -88 72 488 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:inst " "Info: Elaborating entity \"second\" for hierarchy \"second:inst\"" {  } { { "txxclock.bdf" "inst" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 120 32 128 248 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:inst2 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:inst2\"" {  } { { "txxclock.bdf" "inst2" { Schematic "E:/study/EDA/myclock/txxclock/txxclock.bdf" { { 104 776 872 232 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}