second.vhd

VHDL编写的数字钟

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--author:  Suntion Tang  Weixuan Yuan
--date:    2008-5-15 to  5-20
--modify:  By suntion Tang
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library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
entity second is
    port (clk : in std_logic;                     
          s_overflow: out std_logic;                                     
          s_dspl : out std_logic_vector(3 downto 0);  
          s_dsph : out std_logic_vector(3 downto 0) );          
   end ;
architecture behav of second is 
    signal sec1: std_logic_vector(3 downto 0); 
    signal sec2 : std_logic_vector(3 downto 0); 
begin
---------------------------------------------秒十位

s1:process(clk,sec1)

begin

if clk'event and clk='1' then

if (sec1="0101" and sec2="1001")then

sec1<="0000";

else if sec2="1001"then

sec1<=sec1+1;

end if;

end if;
end if;
         if sec1 = 5 then s_overflow<='1';
           else s_overflow<='0';
         end if;
  s_dsph<=sec1;

end process s1;

--------------------------------------------秒个位

s2:process(clk,sec2)

begin

if clk'event and clk='1' then

if sec2="1001" then

sec2<="0000";

else sec2<=sec2+1;

end if;

end if;
  s_dspl<=sec2;
end process s2;

end;