selector12.vhd

VHDL编写的数字钟

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--author:  Suntion Tang  Weixuan Yuan
--date:    2008-5-15 to  5-20
--modify:  By suntion Tang
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selector12 IS
PORT ( s: IN BIT;                                   
          a:  in STD_LOGIC;  
          x : out STD_LOGIC;
          y : OUT STD_LOGIC );
END ;
ARCHITECTURE one OF selector12 IS
BEGIN
PROCESS (a,s)
BEGIN
IF s = '0' THEN
x <= a ; ELSE
y <= a ;
END IF;
END PROCESS;
END ARCHITECTURE one ;