txxclock.map.rpt

VHDL编写的数字钟

+------------------------+-------------+-----------------------------------------+
; Parameter Name         ; Value       ; Type                                    ;
+------------------------+-------------+-----------------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                                 ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                 ;
; LPM_DIRECTION          ; ADD         ; Untyped                                 ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                 ;
; LPM_PIPELINE           ; 0           ; Untyped                                 ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                 ;
; REGISTERED_AT_END      ; 0           ; Untyped                                 ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                 ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                 ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                 ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                      ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                 ;
; USE_WYS                ; OFF         ; Untyped                                 ;
; STYLE                  ; FAST        ; Untyped                                 ;
; CBXI_PARAMETER         ; add_sub_0ih ; Untyped                                 ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                              ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                            ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                            ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                          ;
+------------------------+-------------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 01 17:18:11 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off txxclock -c txxclock
Info: Found 2 design units, including 1 entities, in source file cmp32B.vhd
    Info: Found design unit 1: cmp32B-behav
    Info: Found entity 1: cmp32B
Info: Found 2 design units, including 1 entities, in source file hour.vhd
    Info: Found design unit 1: hour-behav
    Info: Found entity 1: hour
Info: Found 2 design units, including 1 entities, in source file minute.vhd
    Info: Found design unit 1: minute-behav
    Info: Found entity 1: minute
Info: Found 2 design units, including 1 entities, in source file mode.vhd
    Info: Found design unit 1: mode-behav
    Info: Found entity 1: mode
Info: Found 2 design units, including 1 entities, in source file second.vhd
    Info: Found design unit 1: second-behav
    Info: Found entity 1: second
Info: Found 2 design units, including 1 entities, in source file selector.vhd
    Info: Found design unit 1: selector-one
    Info: Found entity 1: selector
Info: Found 2 design units, including 1 entities, in source file selector12.vhd
    Info: Found design unit 1: selector12-one
    Info: Found entity 1: selector12
Info: Found 2 design units, including 1 entities, in source file selector217.vhd
    Info: Found design unit 1: selector217-one
    Info: Found entity 1: selector217
Info: Found 1 design units, including 1 entities, in source file txxclock.bdf
    Info: Found entity 1: txxclock
Info: Elaborating entity "txxclock" for the top level hierarchy
Warning: Port "a" of type selector and instance "inst11" is missing source signal
Info: Elaborating entity "selector" for hierarchy "selector:inst11"
Info: Elaborating entity "cmp32B" for hierarchy "cmp32B:inst7"
Info: Elaborating entity "minute" for hierarchy "minute:inst1"
Info: Elaborating entity "selector12" for hierarchy "selector12:inst10"
Warning (10631): VHDL Process Statement warning at selector12.vhd(19): inferring latch(es) for signal or variable "x", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at selector12.vhd(19): inferring latch(es) for signal or variable "y", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at selector12.vhd(19): inferred latch for "y"
Info (10041): Verilog HDL or VHDL info at selector12.vhd(19): inferred latch for "x"
Info: Elaborating entity "mode" for hierarchy "mode:inst9"
Info: Elaborating entity "second" for hierarchy "second:inst"
Info: Elaborating entity "hour" for hierarchy "hour:inst2"
Info: Elaborating entity "selector217" for hierarchy "selector217:inst6"
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour:inst4|sec2[0]~4"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour:inst2|sec2[0]~4"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "hour:inst4|lpm_counter:sec2_rtl_0"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "hour:inst4|lpm_counter:sec2_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "hour:inst4|lpm_counter:sec2_rtl_0"
Info: Instantiated megafunction "hour:inst4|lpm_counter:sec2_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Instantiated megafunction "second:inst|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Instantiated megafunction "second:inst|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Instantiated megafunction "second:inst|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Instantiated megafunction "second:inst|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "second:inst|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "second:inst|lpm_add_sub:Add0"
Info: Instantiated megafunction "second:inst|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Implemented 141 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 25 output pins
    Info: Implemented 111 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Sun Jun 01 17:18:15 2008
    Info: Elapsed time: 00:00:04