selector217.vhd

VHDL编写的数字钟

-----------------------------------------------------
--author:  Suntion Tang  Weixuan Yuan
--date:    2008-5-15 to  5-20
--modify:  By suntion Tang
-----------------------------------------------------


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY selector217 IS
PORT ( s: IN BIT;                                   
          a: in STD_LOGIC_VECTOR(15 DOWNTO 0);  
          b : in STD_LOGIC_VECTOR(15 DOWNTO 0);
          y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END ;
ARCHITECTURE one OF selector217 IS
BEGIN
PROCESS (a,b,s)
BEGIN
IF s = '0' THEN
y <= a ; ELSE
y <= b ;
END IF;
END PROCESS;
END ARCHITECTURE one ;