cmp32b.vhd

VHDL编写的数字钟

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cmp32B IS
PORT ( 
clk : in STD_LOGIC ;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y : OUT STD_LOGIC );
END ;
ARCHITECTURE behav OF cmp32B IS
BEGIN
process(clk)
begin
IF CLK'EVENT AND CLK = '1' THEN
if A=B then y<='1';
else y<='0';
end if;
end if;
end process;
END behav;