alt_u_div_o5f.tdf

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

	add_sub_30_dataa[25..0]	:	WIRE;
	add_sub_30_datab[25..0]	:	WIRE;
	add_sub_30_result[25..0]	:	WIRE;
	add_sub_31_result_int[26..0]	:	WIRE;
	add_sub_31_cout	:	WIRE;
	add_sub_31_dataa[25..0]	:	WIRE;
	add_sub_31_datab[25..0]	:	WIRE;
	add_sub_31_result[25..0]	:	WIRE;
	add_sub_4_result_int[5..0]	:	WIRE;
	add_sub_4_cout	:	WIRE;
	add_sub_4_dataa[4..0]	:	WIRE;
	add_sub_4_datab[4..0]	:	WIRE;
	add_sub_4_result[4..0]	:	WIRE;
	add_sub_5_result_int[6..0]	:	WIRE;
	add_sub_5_cout	:	WIRE;
	add_sub_5_dataa[5..0]	:	WIRE;
	add_sub_5_datab[5..0]	:	WIRE;
	add_sub_5_result[5..0]	:	WIRE;
	add_sub_6_result_int[7..0]	:	WIRE;
	add_sub_6_cout	:	WIRE;
	add_sub_6_dataa[6..0]	:	WIRE;
	add_sub_6_datab[6..0]	:	WIRE;
	add_sub_6_result[6..0]	:	WIRE;
	add_sub_7_result_int[8..0]	:	WIRE;
	add_sub_7_cout	:	WIRE;
	add_sub_7_dataa[7..0]	:	WIRE;
	add_sub_7_datab[7..0]	:	WIRE;
	add_sub_7_result[7..0]	:	WIRE;
	add_sub_8_result_int[9..0]	:	WIRE;
	add_sub_8_cout	:	WIRE;
	add_sub_8_dataa[8..0]	:	WIRE;
	add_sub_8_datab[8..0]	:	WIRE;
	add_sub_8_result[8..0]	:	WIRE;
	add_sub_9_result_int[10..0]	:	WIRE;
	add_sub_9_cout	:	WIRE;
	add_sub_9_dataa[9..0]	:	WIRE;
	add_sub_9_datab[9..0]	:	WIRE;
	add_sub_9_result[9..0]	:	WIRE;
	DenominatorIn[857..0]	: WIRE;
	DenominatorIn_tmp[857..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[1055..0]	: WIRE;
	NumeratorIn[1055..0]	: WIRE;
	NumeratorIn_tmp[1055..0]	: WIRE;
	prestg[831..0]	: WIRE;
	quotient_tmp[31..0]	: WIRE;
	sel[824..0]	: WIRE;
	selnose[1055..0]	: WIRE;
	StageIn[857..0]	: WIRE;
	StageIn_tmp[857..0]	: WIRE;
	StageOut[831..0]	: WIRE;

BEGIN 
	add_sub_0.dataa[0..0] = NumeratorIn[31..31];
	add_sub_0.datab[0..0] = DenominatorIn[0..0];
	add_sub_1.dataa[] = ( StageIn[26..26], NumeratorIn[62..62]);
	add_sub_1.datab[1..0] = DenominatorIn[27..26];
	add_sub_10_result_int[] = (0, add_sub_10_dataa[]) - (0, add_sub_10_datab[]);
	add_sub_10_result[] = add_sub_10_result_int[10..0];
	add_sub_10_cout = !add_sub_10_result_int[11];
	add_sub_10_dataa[] = ( StageIn[269..260], NumeratorIn[341..341]);
	add_sub_10_datab[] = DenominatorIn[270..260];
	add_sub_11_result_int[] = (0, add_sub_11_dataa[]) - (0, add_sub_11_datab[]);
	add_sub_11_result[] = add_sub_11_result_int[11..0];
	add_sub_11_cout = !add_sub_11_result_int[12];
	add_sub_11_dataa[] = ( StageIn[296..286], NumeratorIn[372..372]);
	add_sub_11_datab[] = DenominatorIn[297..286];
	add_sub_12_result_int[] = (0, add_sub_12_dataa[]) - (0, add_sub_12_datab[]);
	add_sub_12_result[] = add_sub_12_result_int[12..0];
	add_sub_12_cout = !add_sub_12_result_int[13];
	add_sub_12_dataa[] = ( StageIn[323..312], NumeratorIn[403..403]);
	add_sub_12_datab[] = DenominatorIn[324..312];
	add_sub_13_result_int[] = (0, add_sub_13_dataa[]) - (0, add_sub_13_datab[]);
	add_sub_13_result[] = add_sub_13_result_int[13..0];