ps2.fit.qmsg

Vhdl实现的鼠标协议历程

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.220 ns register register " "Info: Estimated most critical path is register to register delay of 11.220 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mouse:u1\|mousey\[0\] 1 REG LAB_X15_Y12 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12; Fanout = 36; REG Node = 'mouse:u1\|mousey\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|mousey[0] } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 332 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.159 ns) + CELL(0.575 ns) 1.734 ns VGA:u2\|Add10~157COUT1 2 COMB LAB_X14_Y10 2 " "Info: 2: + IC(1.159 ns) + CELL(0.575 ns) = 1.734 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'VGA:u2\|Add10~157COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.734 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.814 ns VGA:u2\|Add10~159COUT1 3 COMB LAB_X14_Y10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.814 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'VGA:u2\|Add10~159COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { VGA:u2|Add10~157COUT1 VGA:u2|Add10~159COUT1 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.894 ns VGA:u2\|Add10~163COUT1 4 COMB LAB_X14_Y10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.894 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'VGA:u2\|Add10~163COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { VGA:u2|Add10~159COUT1 VGA:u2|Add10~163COUT1 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.974 ns VGA:u2\|Add10~165COUT1 5 COMB LAB_X14_Y10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.974 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'VGA:u2\|Add10~165COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { VGA:u2|Add10~163COUT1 VGA:u2|Add10~165COUT1 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.582 ns VGA:u2\|Add10~160 6 COMB LAB_X14_Y10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.608 ns) = 2.582 ns; Loc. = LAB_X14_Y10; Fanout = 2; COMB Node = 'VGA:u2\|Add10~160'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { VGA:u2|Add10~165COUT1 VGA:u2|Add10~160 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.304 ns) + CELL(0.292 ns) 4.178 ns VGA:u2\|Equal8~108 7 COMB LAB_X19_Y10 1 " "Info: 7: + IC(1.304 ns) + CELL(0.292 ns) = 4.178 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'VGA:u2\|Equal8~108'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { VGA:u2|Add10~160 VGA:u2|Equal8~108 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.411 ns) + CELL(0.292 ns) 5.881 ns VGA:u2\|Equal8~110 8 COMB LAB_X16_Y13 2 " "Info: 8: + IC(1.411 ns) + CELL(0.292 ns) = 5.881 ns; Loc. = LAB_X16_Y13; Fanout = 2; COMB Node = 'VGA:u2\|Equal8~110'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.703 ns" { VGA:u2|Equal8~108 VGA:u2|Equal8~110 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.590 ns) 7.516 ns VGA:u2\|process7~775 9 COMB LAB_X21_Y13 1 " "Info: 9: + IC(1.045 ns) + CELL(0.590 ns) = 7.516 ns; Loc. = LAB_X21_Y13; Fanout = 1; COMB Node = 'VGA:u2\|process7~775'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.635 ns" { VGA:u2|Equal8~110 VGA:u2|process7~775 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.590 ns) 9.112 ns VGA:u2\|process7~788 10 COMB LAB_X16_Y13 1 " "Info: 10: + IC(1.006 ns) + CELL(0.590 ns) = 9.112 ns; Loc. = LAB_X16_Y13; Fanout = 1; COMB Node = 'VGA:u2\|process7~788'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { VGA:u2|process7~775 VGA:u2|process7~788 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.292 ns) 10.419 ns VGA:u2\|r1~52 11 COMB LAB_X19_Y13 3 " "Info: 11: + IC(1.015 ns) + CELL(0.292 ns) = 10.419 ns; Loc. = LAB_X19_Y13; Fanout = 3; COMB Node = 'VGA:u2\|r1~52'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.307 ns" { VGA:u2|process7~788 VGA:u2|r1~52 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.738 ns) 11.220 ns VGA:u2\|r1 12 REG LAB_X19_Y13 1 " "Info: 12: + IC(0.063 ns) + CELL(0.738 ns) = 11.220 ns; Loc. = LAB_X19_Y13; Fanout = 1; REG Node = 'VGA:u2\|r1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.801 ns" { VGA:u2|r1~52 VGA:u2|r1 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.217 ns ( 37.58 % ) " "Info: Total cell delay = 4.217 ns ( 37.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.003 ns ( 62.42 % ) " "Info: Total interconnect delay = 7.003 ns ( 62.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.220 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 VGA:u2|Add10~159COUT1 VGA:u2|Add10~163COUT1 VGA:u2|Add10~165COUT1 VGA:u2|Add10~160 VGA:u2|Equal8~108 VGA:u2|Equal8~110 VGA:u2|process7~775 VGA:u2|process7~788 VGA:u2|r1~52 VGA:u2|r1 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 8 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 8%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X12_Y11 X23_Y21 " "Info: The peak interconnect region extends from location X12_Y11 to location X23_Y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "reset " "Info: Node reset uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_clk_l " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_clk_l -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_clk_l } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_clk_l } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|fall " "Info: Port clear -- assigned as a global for destination node mouse:u1\|fall -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|fall } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 59 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|fall } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|rise " "Info: Port clear -- assigned as a global for destination node mouse:u1\|rise -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|rise } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 58 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|rise } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_falling_wait " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_falling_wait -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_falling_wait } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_falling_wait } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_clk_h " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_clk_h -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_clk_h } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_clk_h } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_rising_edge " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_rising_edge -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_rising_edge } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_rising_edge } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_falling_edge " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_falling_edge -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_falling_edge } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_falling_edge } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m1_state.m1_rising_wait " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m1_state.m1_rising_wait -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_rising_wait } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 45 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m1_state.m1_rising_wait } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m2_state.m2_reset " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m2_state.m2_reset -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_reset } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_reset } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m2_state.m2_hold_clk_l " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m2_state.m2_hold_clk_l -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_hold_clk_l } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_hold_clk_l } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear mouse:u1\|m2_state.m2_data_low_1 " "Info: Port clear -- assigned as a global for destination node mouse:u1\|m2_state.m2_data_low_1 -- routed using non-global resources" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_data_low_1 } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|m2_state.m2_data_low_1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 7 -1 0 } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "mouse:u1\|m2_state.m2_hold_clk_l " "Info: Following pins have the same output enable: mouse:u1\|m2_state.m2_hold_clk_l" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional m_clk 3.3-V LVTTL " "Info: Type bidirectional pin m_clk uses the 3.3-V LVTTL I/O standard" {  } { { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 9 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "m_clk" } } } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_clk } "NODE_NAME" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_clk } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "mouse:u1\|WideOr15~13 (inverted) " "Info: Following pins have the same output enable: mouse:u1\|WideOr15~13 (inverted)" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional m_data 3.3-V LVTTL " "Info: Type bidirectional pin m_data uses the 3.3-V LVTTL I/O standard" {  } { { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 10 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "m_data" } } } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_data } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 23 17:21:42 2007 " "Info: Processing ended: Sat Jun 23 17:21:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/DLlab07/ps2_mouse/ps2.fit.smsg " "Info: Generated suppressed messages file D:/DLlab07/ps2_mouse/ps2.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}