ps2.tan.qmsg

Vhdl实现的鼠标协议历程

{ "Info" "ITDB_TH_RESULT" "mouse:u1\|m2_state.m2_await_response m_data clk -0.072 ns register " "Info: th for register \"mouse:u1\|m2_state.m2_await_response\" (data pin = \"m_data\", clock pin = \"clk\") is -0.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.408 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns count64:u0\|count\[6\] 2 REG LC_X8_Y10_N6 91 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 91; REG Node = 'count64:u0\|count\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk count64:u0|count[6] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/DLlab07/ps2_mouse/div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns mouse:u1\|m2_state.m2_await_response 3 REG LC_X27_Y14_N8 1 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X27_Y14_N8; Fanout = 1; REG Node = 'mouse:u1\|m2_state.m2_await_response'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { count64:u0|count[6] mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk count64:u0|count[6] mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|m2_state.m2_await_response } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.495 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m_data 1 PIN PIN_166 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_166; Fanout = 1; PIN Node = 'm_data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_data } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns m_data~0 2 COMB IOC_X35_Y16_N1 2 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X35_Y16_N1; Fanout = 2; COMB Node = 'm_data~0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.469 ns" { m_data m_data~0 } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.717 ns) + CELL(0.309 ns) 7.495 ns mouse:u1\|m2_state.m2_await_response 3 REG LC_X27_Y14_N8 1 " "Info: 3: + IC(5.717 ns) + CELL(0.309 ns) = 7.495 ns; Loc. = LC_X27_Y14_N8; Fanout = 1; REG Node = 'mouse:u1\|m2_state.m2_await_response'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.026 ns" { m_data~0 mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 23.72 % ) " "Info: Total cell delay = 1.778 ns ( 23.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.717 ns ( 76.28 % ) " "Info: Total interconnect delay = 5.717 ns ( 76.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { m_data m_data~0 mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { m_data m_data~0 mouse:u1|m2_state.m2_await_response } { 0.000ns 0.000ns 5.717ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk count64:u0|count[6] mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|m2_state.m2_await_response } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { m_data m_data~0 mouse:u1|m2_state.m2_await_response } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { m_data m_data~0 mouse:u1|m2_state.m2_await_response } { 0.000ns 0.000ns 5.717ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "102 " "Info: Allocated 102 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 23 17:22:00 2007 " "Info: Processing ended: Sat Jun 23 17:22:00 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}