ps2.tan.qmsg

Vhdl实现的鼠标协议历程

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "count64:u0\|count\[6\] " "Info: Detected ripple clock \"count64:u0\|count\[6\]\" as buffer" {  } { { "div.vhd" "" { Text "D:/DLlab07/ps2_mouse/div.vhd" 17 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "count64:u0\|count\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "VGA:u2\|clk " "Info: Detected ripple clock \"VGA:u2\|clk\" as buffer" {  } { { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 17 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGA:u2\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mouse:u1\|mousey\[0\] register VGA:u2\|r1 85.83 MHz 11.651 ns Internal " "Info: Clock \"clk\" has Internal fmax of 85.83 MHz between source register \"mouse:u1\|mousey\[0\]\" and destination register \"VGA:u2\|r1\" (period= 11.651 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.794 ns + Longest register register " "Info: + Longest register to register delay is 11.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mouse:u1\|mousey\[0\] 1 REG LC_X15_Y12_N0 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y12_N0; Fanout = 36; REG Node = 'mouse:u1\|mousey\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { mouse:u1|mousey[0] } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 332 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.575 ns) 1.864 ns VGA:u2\|Add10~157COUT1 2 COMB LC_X14_Y10_N0 2 " "Info: 2: + IC(1.289 ns) + CELL(0.575 ns) = 1.864 ns; Loc. = LC_X14_Y10_N0; Fanout = 2; COMB Node = 'VGA:u2\|Add10~157COUT1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.864 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.472 ns VGA:u2\|Add10~158 3 COMB LC_X14_Y10_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.472 ns; Loc. = LC_X14_Y10_N1; Fanout = 3; COMB Node = 'VGA:u2\|Add10~158'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { VGA:u2|Add10~157COUT1 VGA:u2|Add10~158 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.711 ns) + CELL(0.114 ns) 4.297 ns VGA:u2\|Equal8~107 4 COMB LC_X19_Y11_N9 1 " "Info: 4: + IC(1.711 ns) + CELL(0.114 ns) = 4.297 ns; Loc. = LC_X19_Y11_N9; Fanout = 1; COMB Node = 'VGA:u2\|Equal8~107'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.825 ns" { VGA:u2|Add10~158 VGA:u2|Equal8~107 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(0.292 ns) 6.275 ns VGA:u2\|Equal8~110 5 COMB LC_X16_Y13_N0 2 " "Info: 5: + IC(1.686 ns) + CELL(0.292 ns) = 6.275 ns; Loc. = LC_X16_Y13_N0; Fanout = 2; COMB Node = 'VGA:u2\|Equal8~110'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.978 ns" { VGA:u2|Equal8~107 VGA:u2|Equal8~110 } "NODE_NAME" } } { "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/61/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.581 ns) + CELL(0.114 ns) 7.970 ns VGA:u2\|process7~775 6 COMB LC_X21_Y13_N4 1 " "Info: 6: + IC(1.581 ns) + CELL(0.114 ns) = 7.970 ns; Loc. = LC_X21_Y13_N4; Fanout = 1; COMB Node = 'VGA:u2\|process7~775'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.695 ns" { VGA:u2|Equal8~110 VGA:u2|process7~775 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.114 ns) 9.662 ns VGA:u2\|process7~788 7 COMB LC_X16_Y13_N3 1 " "Info: 7: + IC(1.578 ns) + CELL(0.114 ns) = 9.662 ns; Loc. = LC_X16_Y13_N3; Fanout = 1; COMB Node = 'VGA:u2\|process7~788'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { VGA:u2|process7~775 VGA:u2|process7~788 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(0.114 ns) 11.040 ns VGA:u2\|r1~52 8 COMB LC_X19_Y13_N5 3 " "Info: 8: + IC(1.264 ns) + CELL(0.114 ns) = 11.040 ns; Loc. = LC_X19_Y13_N5; Fanout = 3; COMB Node = 'VGA:u2\|r1~52'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.378 ns" { VGA:u2|process7~788 VGA:u2|r1~52 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.309 ns) 11.794 ns VGA:u2\|r1 9 REG LC_X19_Y13_N9 1 " "Info: 9: + IC(0.445 ns) + CELL(0.309 ns) = 11.794 ns; Loc. = LC_X19_Y13_N9; Fanout = 1; REG Node = 'VGA:u2\|r1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.754 ns" { VGA:u2|r1~52 VGA:u2|r1 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.240 ns ( 18.99 % ) " "Info: Total cell delay = 2.240 ns ( 18.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.554 ns ( 81.01 % ) " "Info: Total interconnect delay = 9.554 ns ( 81.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.794 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 VGA:u2|Add10~158 VGA:u2|Equal8~107 VGA:u2|Equal8~110 VGA:u2|process7~775 VGA:u2|process7~788 VGA:u2|r1~52 VGA:u2|r1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.794 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 VGA:u2|Add10~158 VGA:u2|Equal8~107 VGA:u2|Equal8~110 VGA:u2|process7~775 VGA:u2|process7~788 VGA:u2|r1~52 VGA:u2|r1 } { 0.000ns 1.289ns 0.000ns 1.711ns 1.686ns 1.581ns 1.578ns 1.264ns 0.445ns } { 0.000ns 0.575ns 0.608ns 0.114ns 0.292ns 0.114ns 0.114ns 0.114ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.404 ns - Smallest " "Info: - Smallest clock skew is 0.404 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.773 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VGA:u2\|clk 2 REG LC_X9_Y10_N2 30 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X9_Y10_N2; Fanout = 30; REG Node = 'VGA:u2\|clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk VGA:u2|clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.913 ns) + CELL(0.711 ns) 7.773 ns VGA:u2\|r1 3 REG LC_X19_Y13_N9 1 " "Info: 3: + IC(3.913 ns) + CELL(0.711 ns) = 7.773 ns; Loc. = LC_X19_Y13_N9; Fanout = 1; REG Node = 'VGA:u2\|r1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.624 ns" { VGA:u2|clk VGA:u2|r1 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.07 % ) " "Info: Total cell delay = 3.115 ns ( 40.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.658 ns ( 59.93 % ) " "Info: Total interconnect delay = 4.658 ns ( 59.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.773 ns" { clk VGA:u2|clk VGA:u2|r1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.773 ns" { clk clk~out0 VGA:u2|clk VGA:u2|r1 } { 0.000ns 0.000ns 0.745ns 3.913ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.369 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns count64:u0\|count\[6\] 2 REG LC_X8_Y10_N6 91 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 91; REG Node = 'count64:u0\|count\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk count64:u0|count[6] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/DLlab07/ps2_mouse/div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns mouse:u1\|mousey\[0\] 3 REG LC_X15_Y12_N0 36 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X15_Y12_N0; Fanout = 36; REG Node = 'mouse:u1\|mousey\[0\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.220 ns" { count64:u0|count[6] mouse:u1|mousey[0] } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 332 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { clk count64:u0|count[6] mouse:u1|mousey[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|mousey[0] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.773 ns" { clk VGA:u2|clk VGA:u2|r1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.773 ns" { clk clk~out0 VGA:u2|clk VGA:u2|r1 } { 0.000ns 0.000ns 0.745ns 3.913ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { clk count64:u0|count[6] mouse:u1|mousey[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|mousey[0] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 332 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "11.794 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 VGA:u2|Add10~158 VGA:u2|Equal8~107 VGA:u2|Equal8~110 VGA:u2|process7~775 VGA:u2|process7~788 VGA:u2|r1~52 VGA:u2|r1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "11.794 ns" { mouse:u1|mousey[0] VGA:u2|Add10~157COUT1 VGA:u2|Add10~158 VGA:u2|Equal8~107 VGA:u2|Equal8~110 VGA:u2|process7~775 VGA:u2|process7~788 VGA:u2|r1~52 VGA:u2|r1 } { 0.000ns 1.289ns 0.000ns 1.711ns 1.686ns 1.581ns 1.578ns 1.264ns 0.445ns } { 0.000ns 0.575ns 0.608ns 0.114ns 0.292ns 0.114ns 0.114ns 0.114ns 0.309ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.773 ns" { clk VGA:u2|clk VGA:u2|r1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.773 ns" { clk clk~out0 VGA:u2|clk VGA:u2|r1 } { 0.000ns 0.000ns 0.745ns 3.913ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { clk count64:u0|count[6] mouse:u1|mousey[0] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|mousey[0] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "mouse:u1\|q\[32\] m_data clk 1.852 ns register " "Info: tsu for register \"mouse:u1\|q\[32\]\" (data pin = \"m_data\", clock pin = \"clk\") is 1.852 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.184 ns + Longest pin register " "Info: + Longest pin to register delay is 9.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m_data 1 PIN PIN_166 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_166; Fanout = 1; PIN Node = 'm_data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { m_data } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns m_data~0 2 COMB IOC_X35_Y16_N1 2 " "Info: 2: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = IOC_X35_Y16_N1; Fanout = 2; COMB Node = 'm_data~0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.469 ns" { m_data m_data~0 } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.600 ns) + CELL(0.115 ns) 9.184 ns mouse:u1\|q\[32\] 3 REG LC_X14_Y12_N3 1 " "Info: 3: + IC(7.600 ns) + CELL(0.115 ns) = 9.184 ns; Loc. = LC_X14_Y12_N3; Fanout = 1; REG Node = 'mouse:u1\|q\[32\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.715 ns" { m_data~0 mouse:u1|q[32] } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 267 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 17.25 % ) " "Info: Total cell delay = 1.584 ns ( 17.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns ( 82.75 % ) " "Info: Total interconnect delay = 7.600 ns ( 82.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.184 ns" { m_data m_data~0 mouse:u1|q[32] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.184 ns" { m_data m_data~0 mouse:u1|q[32] } { 0.000ns 0.000ns 7.600ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 267 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.369 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns count64:u0\|count\[6\] 2 REG LC_X8_Y10_N6 91 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 91; REG Node = 'count64:u0\|count\[6\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk count64:u0|count[6] } "NODE_NAME" } } { "div.vhd" "" { Text "D:/DLlab07/ps2_mouse/div.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns mouse:u1\|q\[32\] 3 REG LC_X14_Y12_N3 1 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X14_Y12_N3; Fanout = 1; REG Node = 'mouse:u1\|q\[32\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.220 ns" { count64:u0|count[6] mouse:u1|q[32] } "NODE_NAME" } } { "mouse.vhd" "" { Text "D:/DLlab07/ps2_mouse/mouse.vhd" 267 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { clk count64:u0|count[6] mouse:u1|q[32] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|q[32] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.184 ns" { m_data m_data~0 mouse:u1|q[32] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.184 ns" { m_data m_data~0 mouse:u1|q[32] } { 0.000ns 0.000ns 7.600ns } { 0.000ns 1.469ns 0.115ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.369 ns" { clk count64:u0|count[6] mouse:u1|q[32] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.369 ns" { clk clk~out0 count64:u0|count[6] mouse:u1|q[32] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk g VGA:u2\|g1 15.963 ns register " "Info: tco from clock \"clk\" to destination pin \"g\" through register \"VGA:u2\|g1\" is 15.963 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.773 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 7; CLK Node = 'clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns VGA:u2\|clk 2 REG LC_X9_Y10_N2 30 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X9_Y10_N2; Fanout = 30; REG Node = 'VGA:u2\|clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk VGA:u2|clk } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.913 ns) + CELL(0.711 ns) 7.773 ns VGA:u2\|g1 3 REG LC_X19_Y13_N6 1 " "Info: 3: + IC(3.913 ns) + CELL(0.711 ns) = 7.773 ns; Loc. = LC_X19_Y13_N6; Fanout = 1; REG Node = 'VGA:u2\|g1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.624 ns" { VGA:u2|clk VGA:u2|g1 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.07 % ) " "Info: Total cell delay = 3.115 ns ( 40.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.658 ns ( 59.93 % ) " "Info: Total interconnect delay = 4.658 ns ( 59.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.773 ns" { clk VGA:u2|clk VGA:u2|g1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.773 ns" { clk clk~out0 VGA:u2|clk VGA:u2|g1 } { 0.000ns 0.000ns 0.745ns 3.913ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.966 ns + Longest register pin " "Info: + Longest register to pin delay is 7.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA:u2\|g1 1 REG LC_X19_Y13_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y13_N6; Fanout = 1; REG Node = 'VGA:u2\|g1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGA:u2|g1 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.626 ns) + CELL(0.590 ns) 2.216 ns VGA:u2\|g 2 COMB LC_X21_Y9_N2 1 " "Info: 2: + IC(1.626 ns) + CELL(0.590 ns) = 2.216 ns; Loc. = LC_X21_Y9_N2; Fanout = 1; COMB Node = 'VGA:u2\|g'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.216 ns" { VGA:u2|g1 VGA:u2|g } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/DLlab07/ps2_mouse/VGA.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.642 ns) + CELL(2.108 ns) 7.966 ns g 3 PIN PIN_225 0 " "Info: 3: + IC(3.642 ns) + CELL(2.108 ns) = 7.966 ns; Loc. = PIN_225; Fanout = 0; PIN Node = 'g'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.750 ns" { VGA:u2|g g } "NODE_NAME" } } { "ps2.vhd" "" { Text "D:/DLlab07/ps2_mouse/ps2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 33.87 % ) " "Info: Total cell delay = 2.698 ns ( 33.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.268 ns ( 66.13 % ) " "Info: Total interconnect delay = 5.268 ns ( 66.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.966 ns" { VGA:u2|g1 VGA:u2|g g } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.966 ns" { VGA:u2|g1 VGA:u2|g g } { 0.000ns 1.626ns 3.642ns } { 0.000ns 0.590ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.773 ns" { clk VGA:u2|clk VGA:u2|g1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.773 ns" { clk clk~out0 VGA:u2|clk VGA:u2|g1 } { 0.000ns 0.000ns 0.745ns 3.913ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.966 ns" { VGA:u2|g1 VGA:u2|g g } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.966 ns" { VGA:u2|g1 VGA:u2|g g } { 0.000ns 1.626ns 3.642ns } { 0.000ns 0.590ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}