ps2.tan.rpt

Vhdl实现的鼠标协议历程

; N/A   ; None         ; 1.852 ns   ; m_data ; mouse:u1|q[32]                      ; clk      ;
; N/A   ; None         ; 0.442 ns   ; m_clk  ; mouse:u1|m1_state.m1_rising_edge    ; clk      ;
; N/A   ; None         ; 0.440 ns   ; m_clk  ; mouse:u1|m1_state.m1_falling_edge   ; clk      ;
; N/A   ; None         ; 0.439 ns   ; m_clk  ; mouse:u1|m1_state.m1_clk_h          ; clk      ;
; N/A   ; None         ; 0.430 ns   ; m_clk  ; mouse:u1|m1_state.m1_clk_l          ; clk      ;
; N/A   ; None         ; 0.124 ns   ; m_data ; mouse:u1|m2_state.m2_await_response ; clk      ;
+-------+--------------+------------+--------+-------------------------------------+----------+


+-------------------------------------------------------------------------------------------+
; tco                                                                                       ;
+-------+--------------+------------+---------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                            ; To     ; From Clock ;
+-------+--------------+------------+---------------------------------+--------+------------+
; N/A   ; None         ; 15.963 ns  ; VGA:u2|g1                       ; g      ; clk        ;
; N/A   ; None         ; 15.942 ns  ; VGA:u2|hs1                      ; b      ; clk        ;
; N/A   ; None         ; 15.796 ns  ; VGA:u2|vs1                      ; b      ; clk        ;
; N/A   ; None         ; 15.790 ns  ; VGA:u2|vs1                      ; g      ; clk        ;
; N/A   ; None         ; 15.767 ns  ; VGA:u2|r1                       ; r      ; clk        ;
; N/A   ; None         ; 15.625 ns  ; VGA:u2|hs1                      ; g      ; clk        ;
; N/A   ; None         ; 15.544 ns  ; VGA:u2|hs1                      ; r      ; clk        ;
; N/A   ; None         ; 15.450 ns  ; VGA:u2|b1                       ; b      ; clk        ;
; N/A   ; None         ; 14.268 ns  ; VGA:u2|vs1                      ; r      ; clk        ;
; N/A   ; None         ; 13.526 ns  ; mouse:u1|m2_state.m2_data_low_1 ; m_data ; clk        ;
; N/A   ; None         ; 13.041 ns  ; mouse:u1|m2_state.m2_data_low_3 ; m_data ; clk        ;
; N/A   ; None         ; 13.041 ns  ; VGA:u2|hs                       ; hs     ; clk        ;
; N/A   ; None         ; 12.740 ns  ; VGA:u2|vs                       ; vs     ; clk        ;
; N/A   ; None         ; 12.589 ns  ; mouse:u1|m2_state.m2_data_low_2 ; m_data ; clk        ;
; N/A   ; None         ; 12.230 ns  ; mouse:u1|m2_state.m2_hold_clk_l ; m_clk  ; clk        ;
+-------+--------------+------------+---------------------------------+--------+------------+


+---------------------------------------------------------------------------------------------------+
; th                                                                                                ;
+---------------+-------------+-----------+--------+-------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                  ; To Clock ;
+---------------+-------------+-----------+--------+-------------------------------------+----------+
; N/A           ; None        ; -0.072 ns ; m_data ; mouse:u1|m2_state.m2_await_response ; clk      ;
; N/A           ; None        ; -0.378 ns ; m_clk  ; mouse:u1|m1_state.m1_clk_l          ; clk      ;
; N/A           ; None        ; -0.387 ns ; m_clk  ; mouse:u1|m1_state.m1_clk_h          ; clk      ;
; N/A           ; None        ; -0.388 ns ; m_clk  ; mouse:u1|m1_state.m1_falling_edge   ; clk      ;
; N/A           ; None        ; -0.390 ns ; m_clk  ; mouse:u1|m1_state.m1_rising_edge    ; clk      ;
; N/A           ; None        ; -1.800 ns ; m_data ; mouse:u1|q[32]                      ; clk      ;
+---------------+-------------+-----------+--------+-------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Sat Jun 23 17:21:57 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ps2 -c ps2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "count64:u0|count[6]" as buffer
    Info: Detected ripple clock "VGA:u2|clk" as buffer
Info: Clock "clk" has Internal fmax of 85.83 MHz between source register "mouse:u1|mousey[0]" and destination register "VGA:u2|r1" (period= 11.651 ns)
    Info: + Longest register to register delay is 11.794 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y12_N0; Fanout = 36; REG Node = 'mouse:u1|mousey[0]'
        Info: 2: + IC(1.289 ns) + CELL(0.575 ns) = 1.864 ns; Loc. = LC_X14_Y10_N0; Fanout = 2; COMB Node = 'VGA:u2|Add10~157COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.472 ns; Loc. = LC_X14_Y10_N1; Fanout = 3; COMB Node = 'VGA:u2|Add10~158'
        Info: 4: + IC(1.711 ns) + CELL(0.114 ns) = 4.297 ns; Loc. = LC_X19_Y11_N9; Fanout = 1; COMB Node = 'VGA:u2|Equal8~107'
        Info: 5: + IC(1.686 ns) + CELL(0.292 ns) = 6.275 ns; Loc. = LC_X16_Y13_N0; Fanout = 2; COMB Node = 'VGA:u2|Equal8~110'
        Info: 6: + IC(1.581 ns) + CELL(0.114 ns) = 7.970 ns; Loc. = LC_X21_Y13_N4; Fanout = 1; COMB Node = 'VGA:u2|process7~775'
        Info: 7: + IC(1.578 ns) + CELL(0.114 ns) = 9.662 ns; Loc. = LC_X16_Y13_N3; Fanout = 1; COMB Node = 'VGA:u2|process7~788'
        Info: 8: + IC(1.264 ns) + CELL(0.114 ns) = 11.040 ns; Loc. = LC_X19_Y13_N5; Fanout = 3; COMB Node = 'VGA:u2|r1~52'
        Info: 9: + IC(0.445 ns) + CELL(0.309 ns) = 11.794 ns; Loc. = LC_X19_Y13_N9; Fanout = 1; REG Node = 'VGA:u2|r1'
        Info: Total cell delay = 2.240 ns ( 18.99 % )
        Info: Total interconnect delay = 9.554 ns ( 81.01 % )
    Info: - Smallest clock skew is 0.404 ns
        Info: + Shortest clock path from clock "clk" to destination register is 7.773 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.4