keyboard.tan.qmsg

来自「vhdl实现的鼠标协议」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "fclk scancode\[3\] scancode\[3\]\$latch 13.812 ns register " "Info: tco from clock \"fclk\" to destination pin \"scancode\[3\]\" through register \"scancode\[3\]\$latch\" is 13.812 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk source 8.463 ns + Longest register " "Info: + Longest clock path from clock \"fclk\" to source register is 8.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fok 2 REG LC_X12_Y11_N8 8 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X12_Y11_N8; Fanout = 8; REG Node = 'fok'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { fclk fok } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(0.114 ns) 8.463 ns scancode\[3\]\$latch 3 REG LC_X14_Y11_N0 1 " "Info: 3: + IC(5.200 ns) + CELL(0.114 ns) = 8.463 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode\[3\]\$latch'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.314 ns" { fok scancode[3]$latch } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 29.75 % ) " "Info: Total cell delay = 2.518 ns ( 29.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.945 ns ( 70.25 % ) " "Info: Total interconnect delay = 5.945 ns ( 70.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { fclk fok scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { fclk fclk~out0 fok scancode[3]$latch } { 0.000ns 0.000ns 0.745ns 5.200ns } { 0.000ns 1.469ns 0.935ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.349 ns + Longest register pin " "Info: + Longest register to pin delay is 5.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scancode\[3\]\$latch 1 REG LC_X14_Y11_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode\[3\]\$latch'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { scancode[3]$latch } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.225 ns) + CELL(2.124 ns) 5.349 ns scancode\[3\] 2 PIN PIN_16 0 " "Info: 2: + IC(3.225 ns) + CELL(2.124 ns) = 5.349 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'scancode\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.349 ns" { scancode[3]$latch scancode[3] } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 39.71 % ) " "Info: Total cell delay = 2.124 ns ( 39.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.225 ns ( 60.29 % ) " "Info: Total interconnect delay = 3.225 ns ( 60.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.349 ns" { scancode[3]$latch scancode[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.349 ns" { scancode[3]$latch scancode[3] } { 0.000ns 3.225ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { fclk fok scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { fclk fclk~out0 fok scancode[3]$latch } { 0.000ns 0.000ns 0.745ns 5.200ns } { 0.000ns 1.469ns 0.935ns 0.114ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.349 ns" { scancode[3]$latch scancode[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.349 ns" { scancode[3]$latch scancode[3] } { 0.000ns 3.225ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "clk1 clkin fclk -6.214 ns register " "Info: th for register \"clk1\" (data pin = \"clkin\", clock pin = \"fclk\") is -6.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"fclk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns clk1 2 REG LC_X12_Y11_N0 5 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y11_N0; Fanout = 5; REG Node = 'clk1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { fclk clk1 } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk clk1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 clk1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.154 ns - Shortest pin register " "Info: - Shortest pin to register delay is 9.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 PIN PIN_167 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_167; Fanout = 1; PIN Node = 'clkin'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.570 ns) + CELL(0.115 ns) 9.154 ns clk1 2 REG LC_X12_Y11_N0 5 " "Info: 2: + IC(7.570 ns) + CELL(0.115 ns) = 9.154 ns; Loc. = LC_X12_Y11_N0; Fanout = 5; REG Node = 'clk1'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.685 ns" { clkin clk1 } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 17.30 % ) " "Info: Total cell delay = 1.584 ns ( 17.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.570 ns ( 82.70 % ) " "Info: Total interconnect delay = 7.570 ns ( 82.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.154 ns" { clkin clk1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.154 ns" { clkin clkin~out0 clk1 } { 0.000ns 0.000ns 7.570ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk clk1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 clk1 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.154 ns" { clkin clk1 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.154 ns" { clkin clkin~out0 clk1 } { 0.000ns 0.000ns 7.570ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 12 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 15 22:40:47 2008 " "Info: Processing ended: Tue Apr 15 22:40:47 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}