keyboard.tan.qmsg

来自「vhdl实现的鼠标协议」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fok " "Info: Detected ripple clock \"fok\" as buffer" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "fok" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "fclk register code\[4\] register state.stop 269.4 MHz 3.712 ns Internal " "Info: Clock \"fclk\" has Internal fmax of 269.4 MHz between source register \"code\[4\]\" and destination register \"state.stop\" (period= 3.712 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.451 ns + Longest register register " "Info: + Longest register to register delay is 3.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns code\[4\] 1 REG LC_X13_Y11_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y11_N2; Fanout = 3; REG Node = 'code\[4\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[4] } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.442 ns) 1.600 ns process0~56 2 COMB LC_X13_Y11_N0 1 " "Info: 2: + IC(1.158 ns) + CELL(0.442 ns) = 1.600 ns; Loc. = LC_X13_Y11_N0; Fanout = 1; COMB Node = 'process0~56'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { code[4] process0~56 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 2.441 ns process0~57 3 COMB LC_X13_Y11_N4 2 " "Info: 3: + IC(0.399 ns) + CELL(0.442 ns) = 2.441 ns; Loc. = LC_X13_Y11_N4; Fanout = 2; COMB Node = 'process0~57'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { process0~56 process0~57 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.309 ns) 3.451 ns state.stop 4 REG LC_X12_Y11_N4 3 " "Info: 4: + IC(0.701 ns) + CELL(0.309 ns) = 3.451 ns; Loc. = LC_X12_Y11_N4; Fanout = 3; REG Node = 'state.stop'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.010 ns" { process0~57 state.stop } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.193 ns ( 34.57 % ) " "Info: Total cell delay = 1.193 ns ( 34.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.258 ns ( 65.43 % ) " "Info: Total interconnect delay = 2.258 ns ( 65.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.451 ns" { code[4] process0~56 process0~57 state.stop } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.451 ns" { code[4] process0~56 process0~57 state.stop } { 0.000ns 1.158ns 0.399ns 0.701ns } { 0.000ns 0.442ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"fclk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state.stop 2 REG LC_X12_Y11_N4 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y11_N4; Fanout = 3; REG Node = 'state.stop'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { fclk state.stop } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk state.stop } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 state.stop } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"fclk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns code\[4\] 2 REG LC_X13_Y11_N2 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N2; Fanout = 3; REG Node = 'code\[4\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { fclk code[4] } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[4] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk state.stop } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 state.stop } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[4] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.451 ns" { code[4] process0~56 process0~57 state.stop } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.451 ns" { code[4] process0~56 process0~57 state.stop } { 0.000ns 1.158ns 0.399ns 0.701ns } { 0.000ns 0.442ns 0.442ns 0.309ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk state.stop } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 state.stop } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[4] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[4] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "fclk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"fclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "code\[3\] scancode\[3\]\$latch fclk 4.468 ns " "Info: Found hold time violation between source  pin or register \"code\[3\]\" and destination pin or register \"scancode\[3\]\$latch\" for clock \"fclk\" (Hold time is 4.468 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.538 ns + Largest " "Info: + Largest clock skew is 5.538 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 8.463 ns + Longest register " "Info: + Longest clock path from clock \"fclk\" to destination register is 8.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fok 2 REG LC_X12_Y11_N8 8 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X12_Y11_N8; Fanout = 8; REG Node = 'fok'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { fclk fok } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.200 ns) + CELL(0.114 ns) 8.463 ns scancode\[3\]\$latch 3 REG LC_X14_Y11_N0 1 " "Info: 3: + IC(5.200 ns) + CELL(0.114 ns) = 8.463 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode\[3\]\$latch'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.314 ns" { fok scancode[3]$latch } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.518 ns ( 29.75 % ) " "Info: Total cell delay = 2.518 ns ( 29.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.945 ns ( 70.25 % ) " "Info: Total interconnect delay = 5.945 ns ( 70.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { fclk fok scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { fclk fclk~out0 fok scancode[3]$latch } { 0.000ns 0.000ns 0.745ns 5.200ns } { 0.000ns 1.469ns 0.935ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"fclk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns code\[3\] 2 REG LC_X14_Y11_N2 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N2; Fanout = 3; REG Node = 'code\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { fclk code[3] } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[3] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { fclk fok scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { fclk fclk~out0 fok scancode[3]$latch } { 0.000ns 0.000ns 0.745ns 5.200ns } { 0.000ns 1.469ns 0.935ns 0.114ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[3] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.846 ns - Shortest register register " "Info: - Shortest register to register delay is 0.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns code\[3\] 1 REG LC_X14_Y11_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N2; Fanout = 3; REG Node = 'code\[3\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { code[3] } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.292 ns) 0.846 ns scancode\[3\]\$latch 2 REG LC_X14_Y11_N0 1 " "Info: 2: + IC(0.554 ns) + CELL(0.292 ns) = 0.846 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode\[3\]\$latch'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { code[3] scancode[3]$latch } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.292 ns ( 34.52 % ) " "Info: Total cell delay = 0.292 ns ( 34.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.554 ns ( 65.48 % ) " "Info: Total interconnect delay = 0.554 ns ( 65.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { code[3] scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.846 ns" { code[3] scancode[3]$latch } { 0.000ns 0.554ns } { 0.000ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 34 -1 0 } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 30 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.463 ns" { fclk fok scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "8.463 ns" { fclk fclk~out0 fok scancode[3]$latch } { 0.000ns 0.000ns 0.745ns 5.200ns } { 0.000ns 1.469ns 0.935ns 0.114ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk code[3] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 code[3] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.846 ns" { code[3] scancode[3]$latch } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "0.846 ns" { code[3] scancode[3]$latch } { 0.000ns 0.554ns } { 0.000ns 0.292ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data datain fclk 6.270 ns register " "Info: tsu for register \"data\" (data pin = \"datain\", clock pin = \"fclk\") is 6.270 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.158 ns + Longest pin register " "Info: + Longest pin to register delay is 9.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datain 1 PIN PIN_166 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_166; Fanout = 1; PIN Node = 'datain'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.574 ns) + CELL(0.115 ns) 9.158 ns data 2 REG LC_X13_Y11_N4 13 " "Info: 2: + IC(7.574 ns) + CELL(0.115 ns) = 9.158 ns; Loc. = LC_X13_Y11_N4; Fanout = 13; REG Node = 'data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.689 ns" { datain data } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 17.30 % ) " "Info: Total cell delay = 1.584 ns ( 17.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.574 ns ( 82.70 % ) " "Info: Total interconnect delay = 7.574 ns ( 82.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.158 ns" { datain data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.158 ns" { datain datain~out0 data } { 0.000ns 0.000ns 7.574ns } { 0.000ns 1.469ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fclk destination 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"fclk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fclk 1 CLK PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { fclk } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns data 2 REG LC_X13_Y11_N4 13 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N4; Fanout = 13; REG Node = 'data'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { fclk data } "NODE_NAME" } } { "Keyboard.vhd" "" { Text "D:/DL08/Demo/upload/程序范例/psKeyboard/Keyboard.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 data } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.158 ns" { datain data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.158 ns" { datain datain~out0 data } { 0.000ns 0.000ns 7.574ns } { 0.000ns 1.469ns 0.115ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { fclk data } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { fclk fclk~out0 data } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}