keyboard.tan.rpt

vhdl实现的鼠标协议

+-------+--------------+------------+-------------------+-------------+------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+--------+------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To   ; To Clock ;
+---------------+-------------+-----------+--------+------+----------+
; N/A           ; None        ; -6.214 ns ; clkin  ; clk1 ; fclk     ;
; N/A           ; None        ; -6.218 ns ; datain ; data ; fclk     ;
+---------------+-------------+-----------+--------+------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 15 22:40:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Keyboard -c Keyboard --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "scancode[0]$latch" is a latch
    Warning: Node "scancode[1]$latch" is a latch
    Warning: Node "scancode[2]$latch" is a latch
    Warning: Node "scancode[3]$latch" is a latch
    Warning: Node "scancode[4]$latch" is a latch
    Warning: Node "scancode[5]$latch" is a latch
    Warning: Node "scancode[6]$latch" is a latch
    Warning: Node "scancode[7]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "fclk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "fok" as buffer
Info: Clock "fclk" has Internal fmax of 269.4 MHz between source register "code[4]" and destination register "state.stop" (period= 3.712 ns)
    Info: + Longest register to register delay is 3.451 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y11_N2; Fanout = 3; REG Node = 'code[4]'
        Info: 2: + IC(1.158 ns) + CELL(0.442 ns) = 1.600 ns; Loc. = LC_X13_Y11_N0; Fanout = 1; COMB Node = 'process0~56'
        Info: 3: + IC(0.399 ns) + CELL(0.442 ns) = 2.441 ns; Loc. = LC_X13_Y11_N4; Fanout = 2; COMB Node = 'process0~57'
        Info: 4: + IC(0.701 ns) + CELL(0.309 ns) = 3.451 ns; Loc. = LC_X12_Y11_N4; Fanout = 3; REG Node = 'state.stop'
        Info: Total cell delay = 1.193 ns ( 34.57 % )
        Info: Total interconnect delay = 2.258 ns ( 65.43 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "fclk" to destination register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y11_N4; Fanout = 3; REG Node = 'state.stop'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
        Info: - Longest clock path from clock "fclk" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N2; Fanout = 3; REG Node = 'code[4]'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "fclk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "code[3]" and destination pin or register "scancode[3]$latch" for clock "fclk" (Hold time is 4.468 ns)
    Info: + Largest clock skew is 5.538 ns
        Info: + Longest clock path from clock "fclk" to destination register is 8.463 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
            Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X12_Y11_N8; Fanout = 8; REG Node = 'fok'
            Info: 3: + IC(5.200 ns) + CELL(0.114 ns) = 8.463 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode[3]$latch'
            Info: Total cell delay = 2.518 ns ( 29.75 % )
            Info: Total interconnect delay = 5.945 ns ( 70.25 % )
        Info: - Shortest clock path from clock "fclk" to source register is 2.925 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
            Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N2; Fanout = 3; REG Node = 'code[3]'
            Info: Total cell delay = 2.180 ns ( 74.53 % )
            Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: - Micro clock to output delay of source is 0.224 ns
    Info: - Shortest register to register delay is 0.846 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N2; Fanout = 3; REG Node = 'code[3]'
        Info: 2: + IC(0.554 ns) + CELL(0.292 ns) = 0.846 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode[3]$latch'
        Info: Total cell delay = 0.292 ns ( 34.52 % )
        Info: Total interconnect delay = 0.554 ns ( 65.48 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "data" (data pin = "datain", clock pin = "fclk") is 6.270 ns
    Info: + Longest pin to register delay is 9.158 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_166; Fanout = 1; PIN Node = 'datain'
        Info: 2: + IC(7.574 ns) + CELL(0.115 ns) = 9.158 ns; Loc. = LC_X13_Y11_N4; Fanout = 13; REG Node = 'data'
        Info: Total cell delay = 1.584 ns ( 17.30 % )
        Info: Total interconnect delay = 7.574 ns ( 82.70 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "fclk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N4; Fanout = 13; REG Node = 'data'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
Info: tco from clock "fclk" to destination pin "scancode[3]" through register "scancode[3]$latch" is 13.812 ns
    Info: + Longest clock path from clock "fclk" to source register is 8.463 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
        Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X12_Y11_N8; Fanout = 8; REG Node = 'fok'
        Info: 3: + IC(5.200 ns) + CELL(0.114 ns) = 8.463 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode[3]$latch'
        Info: Total cell delay = 2.518 ns ( 29.75 % )
        Info: Total interconnect delay = 5.945 ns ( 70.25 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 5.349 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N0; Fanout = 1; REG Node = 'scancode[3]$latch'
        Info: 2: + IC(3.225 ns) + CELL(2.124 ns) = 5.349 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'scancode[3]'
        Info: Total cell delay = 2.124 ns ( 39.71 % )
        Info: Total interconnect delay = 3.225 ns ( 60.29 % )
Info: th for register "clk1" (data pin = "clkin", clock pin = "fclk") is -6.214 ns
    Info: + Longest clock path from clock "fclk" to destination register is 2.925 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; CLK Node = 'fclk'
        Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y11_N0; Fanout = 5; REG Node = 'clk1'
        Info: Total cell delay = 2.180 ns ( 74.53 % )
        Info: Total interconnect delay = 0.745 ns ( 25.47 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 9.154 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_167; Fanout = 1; PIN Node = 'clkin'
        Info: 2: + IC(7.570 ns) + CELL(0.115 ns) = 9.154 ns; Loc. = LC_X12_Y11_N0; Fanout = 5; REG Node = 'clk1'
        Info: Total cell delay = 1.584 ns ( 17.30 % )
        Info: Total interconnect delay = 7.570 ns ( 82.70 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 12 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Tue Apr 15 22:40:47 2008
    Info: Elapsed time: 00:00:01