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📄 keyboard.map.rpt

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; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 39    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 22    ;
;                                             ;       ;
; Total registers                             ; 25    ;
; I/O pins                                    ; 0     ;
; Maximum fan-out node                        ; fclk  ;
; Maximum fan-out                             ; 25    ;
; Total fan-out                               ; 172   ;
; Average fan-out                             ; 3.37  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |Keyboard                  ; 39 (39)     ; 25           ; 0           ; 0    ; 0            ; 14 (14)      ; 12 (12)           ; 13 (13)          ; 0 (0)           ; 0 (0)      ; |Keyboard           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Keyboard|state                                                                                                                                             ;
+--------------+--------------+------------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-------------+-------------+
; Name         ; state.finish ; state.stop ; state.parity ; state.d7 ; state.d6 ; state.d5 ; state.d4 ; state.d3 ; state.d2 ; state.d1 ; state.d0 ; state.start ; state.delay ;
+--------------+--------------+------------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-------------+-------------+
; state.delay  ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 0           ;
; state.start  ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1           ; 1           ;
; state.d0     ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0           ; 1           ;
; state.d1     ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0           ; 1           ;
; state.d2     ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0           ; 1           ;
; state.d3     ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.d4     ; 0            ; 0          ; 0            ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.d5     ; 0            ; 0          ; 0            ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.d6     ; 0            ; 0          ; 0            ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.d7     ; 0            ; 0          ; 0            ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.parity ; 0            ; 0          ; 1            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.stop   ; 0            ; 1          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
; state.finish ; 1            ; 0          ; 0            ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0           ; 1           ;
+--------------+--------------+------------+--------------+----------+----------+----------+----------+----------+----------+----------+----------+-------------+-------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; scancode[0]$latch                                  ; fok                 ; yes                    ;
; scancode[1]$latch                                  ; fok                 ; yes                    ;
; scancode[2]$latch                                  ; fok                 ; yes                    ;
; scancode[3]$latch                                  ; fok                 ; yes                    ;
; scancode[4]$latch                                  ; fok                 ; yes                    ;
; scancode[5]$latch                                  ; fok                 ; yes                    ;
; scancode[6]$latch                                  ; fok                 ; yes                    ;
; scancode[7]$latch                                  ; fok                 ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 25    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 22    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 15 22:40:25 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Keyboard -c Keyboard
Info: Found 2 design units, including 1 entities, in source file Keyboard.vhd
    Info: Found design unit 1: Keyboard-rtl
    Info: Found entity 1: Keyboard
Info: Elaborating entity "Keyboard" for the top level hierarchy
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[0]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[1]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[2]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[3]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[4]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[5]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[6]"
Info (10041): Verilog HDL or VHDL info at Keyboard.vhd(30): inferred latch for "scancode[7]"
Info: State machine "|Keyboard|state" contains 13 states
Info: Selected Auto state machine encoding method for state machine "|Keyboard|state"
Info: Encoding result for state machine "|Keyboard|state"
    Info: Completed encoding using 13 state bits
        Info: Encoded state bit "state.finish"
        Info: Encoded state bit "state.stop"
        Info: Encoded state bit "state.parity"
        Info: Encoded state bit "state.d7"
        Info: Encoded state bit "state.d6"
        Info: Encoded state bit "state.d5"
        Info: Encoded state bit "state.d4"
        Info: Encoded state bit "state.d3"
        Info: Encoded state bit "state.d2"
        Info: Encoded state bit "state.d1"
        Info: Encoded state bit "state.d0"
        Info: Encoded state bit "state.start"
        Info: Encoded state bit "state.delay"
    Info: State "|Keyboard|state.delay" uses code string "0000000000000"
    Info: State "|Keyboard|state.start" uses code string "0000000000011"
    Info: State "|Keyboard|state.d0" uses code string "0000000000101"
    Info: State "|Keyboard|state.d1" uses code string "0000000001001"
    Info: State "|Keyboard|state.d2" uses code string "0000000010001"
    Info: State "|Keyboard|state.d3" uses code string "0000000100001"
    Info: State "|Keyboard|state.d4" uses code string "0000001000001"
    Info: State "|Keyboard|state.d5" uses code string "0000010000001"
    Info: State "|Keyboard|state.d6" uses code string "0000100000001"
    Info: State "|Keyboard|state.d7" uses code string "0001000000001"
    Info: State "|Keyboard|state.parity" uses code string "0010000000001"
    Info: State "|Keyboard|state.stop" uses code string "0100000000001"
    Info: State "|Keyboard|state.finish" uses code string "1000000000001"
Info: Implemented 51 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 8 output pins
    Info: Implemented 39 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Tue Apr 15 22:40:28 2008
    Info: Elapsed time: 00:00:03


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