deb_i2c.map.rpt

I2C总线的verilog 程序

; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+
; 10:1               ; 4 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[7]         ;
; 10:1               ; 3 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; Yes        ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_buf[3]         ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |deb_i2c|i2c_top:inst|hc164_driver:hc164_driver_inst|Selector1 ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; No         ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8in_state~20        ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|head_state~14         ;
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|Selector48            ;
; 11:1               ; 2 bits    ; 14 LEs        ; 6 LEs                ; 8 LEs                  ; No         ; |deb_i2c|i2c_top:inst|i2c_wr:i2c_wr_inst|sh8out_state~54       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------+


+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: i2c_top:inst ;
+----------------+---------+--------------------------------+
; Parameter Name ; Value   ; Type                           ;
+----------------+---------+--------------------------------+
; IDLE           ; 0000001 ; Binary                         ;
; WR_BYTE        ; 0000010 ; Binary                         ;
; WR_ACK         ; 0000100 ; Binary                         ;
; DELAY          ; 0001000 ; Binary                         ;
; RD_BYTE        ; 0010000 ; Binary                         ;
; RD_ACK         ; 0100000 ; Binary                         ;
; SHOW           ; 1000000 ; Binary                         ;
+----------------+---------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: i2c_top:inst|i2c_wr:i2c_wr_inst ;
+----------------+-------------+-----------------------------------------------+
; Parameter Name ; Value       ; Type                                          ;
+----------------+-------------+-----------------------------------------------+
; Idle           ; 00000000001 ; Binary                                        ;
; Ready          ; 00000000010 ; Binary                                        ;
; Write_start    ; 00000000100 ; Binary                                        ;
; Ctrl_write     ; 00000001000 ; Binary                                        ;
; Addr_write     ; 00000010000 ; Binary                                        ;
; Data_write     ; 00000100000 ; Binary                                        ;
; Read_start     ; 00001000000 ; Binary                                        ;
; Ctrl_read      ; 00010000000 ; Binary                                        ;
; Data_read      ; 00100000000 ; Binary                                        ;
; Stop           ; 01000000000 ; Binary                                        ;
; Ackn           ; 10000000000 ; Binary                                        ;
; sh8out_bit7    ; 000000001   ; Binary                                        ;
; sh8out_bit6    ; 000000010   ; Binary                                        ;
; sh8out_bit5    ; 000000100   ; Binary                                        ;
; sh8out_bit4    ; 000001000   ; Binary                                        ;
; sh8out_bit3    ; 000010000   ; Binary                                        ;
; sh8out_bit2    ; 000100000   ; Binary                                        ;
; sh8out_bit1    ; 001000000   ; Binary                                        ;
; sh8out_bit0    ; 010000000   ; Binary                                        ;
; sh8out_end     ; 100000000   ; Binary                                        ;
; sh8in_begin    ; 0000000001  ; Binary                                        ;
; sh8in_bit7     ; 0000000010  ; Binary                                        ;
; sh8in_bit6     ; 0000000100  ; Binary                                        ;
; sh8in_bit5     ; 0000001000  ; Binary                                        ;
; sh8in_bit4     ; 0000010000  ; Binary                                        ;
; sh8in_bit3     ; 0000100000  ; Binary                                        ;
; sh8in_bit2     ; 0001000000  ; Binary                                        ;
; sh8in_bit1     ; 0010000000  ; Binary                                        ;
; sh8in_bit0     ; 0100000000  ; Binary                                        ;
; sh8in_end      ; 1000000000  ; Binary                                        ;
; head_begin     ; 001         ; Binary                                        ;
; head_bit       ; 010         ; Binary                                        ;
; head_end       ; 100         ; Binary                                        ;
; stop_begin     ; 001         ; Binary                                        ;
; stop_bit       ; 010         ; Binary                                        ;
; stop_end       ; 100         ; Binary                                        ;
; YES            ; 1           ; Integer                                       ;
; NO             ; 0           ; Integer                                       ;
+----------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version
    Info: Processing started: Tue Jan 30 16:34:37 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off deb_i2c -c deb_i2c
Info: Found 1 design units, including 1 entities, in source file i2c_top.v
    Info: Found entity 1: i2c_top
Info: Found 1 design units, including 1 entities, in source file i2c_wr.v
    Info: Found entity 1: i2c_wr
Warning: Can't analyze file -- file D:/altera_6/works/ep2c8/I2C/seg_display.v is missing
Info: Found 1 design units, including 1 entities, in source file deb_i2c.bdf
    Info: Found entity 1: deb_i2c
Info: Elaborating entity "deb_i2c" for the top level hierarchy
Info: Elaborating entity "i2c_top" for hierarchy "i2c_top:inst"
Info: Elaborating entity "i2c_wr" for hierarchy "i2c_top:inst|i2c_wr:i2c_wr_inst"
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(110): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(111): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(112): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(113): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(127): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(128): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(129): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(130): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(151): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(152): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(153): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(154): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(438): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(439): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(440): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(457): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(458): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(168): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(169): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(354): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(355): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(363): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(364): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(421): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(422): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(210): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(220): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(221): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(222): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(232): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(233): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(244): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(245): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(472): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(473): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(474): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(488): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c_wr.v(489): truncated value with size 32 to match size of target (1)