anal.out
来自「xilinx 开发板程序」· OUT 代码 · 共 4 行
OUT
4 行
Loading db file 'H:/fndtn/SYNTH/lib/libraries/syn/gtech.db'
Reading in the Synopsys vhdl primitives.
F:/XESSCORP/ELASCOMP/XSBRDS/designs/VGAVHDL/vgacore.vhd:
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