test_dualport.ucf

xilinx 开发板原程序

# XSA Board FPGA pin assignment constraints

NET      "clk"     TNM_NET  =      "clk"; 
TIMESPEC "TS_clk"  =        PERIOD "clk"  10 ns HIGH 50 %; 

# Manually assign locations for the DCMs along the bottom of the FPGA
# because PAR sometimes places them in opposing corners and that ruins the clocks.
INST "u0_u2_dllint" LOC="DCM_X0Y0";
INST "u0_u2_dllext" LOC="DCM_X1Y0";

# SDRAM memory tester pin assignments
net      ce_n      loc=R4;  # Flash RAM chip-enable
net      sw2       loc=E11; # active-low pushbutton
net      clk       loc=T9;  # main clock
net      sclkfb    loc=N8;  # feedback SDRAM clock after PCB delays
net      sclk      loc=E10; # clock to SDRAM
net      cke       loc=D7;  # SDRAM clock enable
net      cs_n      loc=B8;  # SDRAM chip-select
net      ras_n     loc=A9;  
net      cas_n     loc=A10; 
net      we_n      loc=B10; 
net      ba<0>     loc=A7;  
net      ba<1>     loc=C7;  
net      sAddr<0>  loc=B5;  
net      sAddr<1>  loc=A4;  
net      sAddr<2>  loc=B4;  
net      sAddr<3>  loc=E6;  
net      sAddr<4>  loc=E3;  
net      sAddr<5>  loc=C1;  
net      sAddr<6>  loc=E4;  
net      sAddr<7>  loc=D3;  
net      sAddr<8>  loc=C2;  
net      sAddr<9>  loc=A3;  
net      sAddr<10> loc=B6;  
net      sAddr<11> loc=C5;  
net      sAddr<12> loc=C6;  
net      sData<0>  loc=C15; 
net      sData<1>  loc=D12; 
net      sData<2>  loc=A14; 
net      sData<3>  loc=B13; 
net      sData<4>  loc=D11; 
net      sData<5>  loc=A12; 
net      sData<6>  loc=C11; 
net      sData<7>  loc=D10; 
net      sData<8>  loc=B11; 
net      sData<9>  loc=B12; 
net      sData<10> loc=C12; 
net      sData<11> loc=B14; 
net      sData<12> loc=D14; 
net      sData<13> loc=C16; 
net      sData<14> loc=F12; 
net      sData<15> loc=F13; 
net      dqmh      loc=D9;  
net      dqml      loc=C10; 
net      s<0>      loc=M6;  
net      s<1>      loc=M11; 
net      s<2>      loc=N6;  
net      s<3>      loc=R7;  
net      s<4>      loc=P10; 
net      s<5>      loc=T7;  
net      s<6>      loc=R10; 
net      pps<6>    loc=T10;