test_dualport.npl

xilinx 开发板原程序

JDF G
// Created by Project Navigator ver 1.0
PROJECT test_dualport
DESIGN test_dualport
DEVFAM spartan2e
DEVFAMTIME 1047971102
DEVICE xc2s300e
DEVICETIME 1047971102
DEVPKG pq208
DEVPKGTIME 1047971102
DEVSPEED -6
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE test_dualport.vhd
SOURCE ..\..\..\XS_LIB\sdramcntl.vhd
SOURCE ..\..\..\XS_LIB\memtest.vhd
SOURCE ..\..\..\XS_LIB\randgen.vhd
SOURCE ..\..\..\XS_LIB\common.vhd
SOURCE ..\..\XSB_LIB\test_dualport_core.vhd
DEPASSOC test_dualport test_dualport.ucf
[Normal]
p_ModelSimSimRunTime_tbw=xstvhd, spartan2, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
[STATUS-ALL]
test_dualport.ncdFile=WARNINGS,1119037548
test_dualport.ngcFile=WARNINGS,1119037516
[STRATEGY-LIST]
Normal=True