aldec.ini

xilinx 开发板程序

[Paths]
Enable Warning Dialogs=On
Smart FE=On
Revision Naming Convention=rev
EXE=C:\FNDTN\ACTIVE\EXE
LIBDIR=C:\FNDTN\ACTIVE
LibID=C:\FNDTN\ACTIVE
SYSLIB=C:\FNDTN\ACTIVE\SYSLIB
PROJECTS=C:\FNDTN\ACTIVE\PROJECTS\
VHDLDat=C:\FNDTN\ACTIVE\VHDL\
Editor=C:\UTILS\PFE32.EXE

[Net Attributes]
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU=
COLLAPSE=
KEEP=
NOREDUCE=
PERIOD=
PWR_MODE=
S=
TIG=
TNM=
TPSYNC=
TPTHRU=

[Schematic]
Grid Color=8
Select Color=12
Select Wire Color=12
Pin Name Color=9
Pin Number Color=12
Symbol Name Color=2
Symbol Reference Color=2
Symbol Parameters Color=0
Symbol Technology Color=13
Symbol Color I=0
Symbol Color II=7
Symbol Color (empty)=4
Symbol Color (netlist)=5
Symbol Color (schematic)=1
Switch Symbol Color=12
Wire Color=9
Wire Edit Color=0
Junction Color=11
LogiBlox Pin Color=2
In Line Net Name Color=9
Net Name Color=2
PWR Color=0
Terminal Color=0
Terminal Name Color=2
Bus Color=4
Bus Name Color=2
Bus Tap Color=1
Default Graphics Color=0
Background Color=0
Pin Font=0
Pin Font Face=0
Symbol Name=1
Symbol Name Face=0
Symbol Reference=1
Symbol Reference Face=0
Symbol Parameters=1
Symbol Parameters Face=0
Net Name=1
Net Name Face=0
Terminal Name=1
Terminal Name Face=0
Bus Name=1
Bus Name Face=0
Graphics Font=0
Graphics Font Face=0
Small Font Height=20
Regular Font Height=35
Large Font Height=50
Visible Font Minimal Height=5
Wire Line Style=1
Wire Line Width=1
Junction Size=8
Junction Type=0
Xblox Wire Line Style=1
Xblox Wire Line Width=8
Xblox Junction Size=12
Xblox Junction Type=0
Autorouting time (sec/wire)=10
Wire Correction=ON
Check Pin Type=ON
Orthogonal Wires=ON
Autorouting=ON
Check Chip Crossing=ON
Bus Line Width=8
Bus Tap Type=3
Bus Left Range=7
Bus Right Range=0
Bus Corners=OFF
Symbol Line Style I=1
Symbol Line Style II=1
Graphics Line Style=1
Automatic Backup (min)=5
Symbol AutoBox Width=4
Allow symbol overlap=ON
Allow wires overlap=ON
Thick Line Width=7
Simulation step (ns)=0
Interactive mode=ON
Defer to audit file=OFF
Internal Warnings=OFF
Snap to Grid=ON
Create TEMP Symbols=ON
Delete Wires with Symbol=OFF
Status Line=ON
Command Line=ON
Coordinates=ON
Button Menu=ON
Button Horizontal=3
Ruler=OFF
Ruler Mark=2
Ruler Mark Width=1
Graphics=ON
Table=ON
Symbol Text=ON
Beep on Error=ON
Print frame=ON
Print 4 page tile=1
Printing margin=5
Print copies=1
Print whole project=1
Print All Black=ON
Sheet Format=18
Vertical Zones=8
Horizontal Zones=8
Grid Active=OFF
Grid Step=4
Grid Style=0
CrossHair Cursor=OFF
Maximized=ON
Window=196, 12, 964, 549
Save on Exit=ON
hidden pins=OFF
view_references=OFF
hide_references=OFF
drc_floating_nets=ON
drc_bus_match_pin=ON
drc_unconnected_input_pin=ON
drc_unconnected_output_pin=ON
drc_bustap_match_bus=ON
drc_bus_name=ON
drc_outputs_connected=ON
drc_references=ON
drc_loadless_net=ON
drc_sourceless_net=ON
drc_pin_without_terminal=ON
drc_root_terminals=ON
drc_buble_at_pin=ON
drc_recursion=OFF
drc_check=ON
Raster On=ON
Add Libraries=OFF
Table01=Project
Table02=Sheet
Table03=Date
Table04=Date Last Modified

[SC_ALV_options]
recursive=YES
ignore_builtin=NO
remove_busbox=YES
autopinname=YES
autopin=YES
xblox_bus=YES
invisible_refname=NO
ignore_internal_prop=YES

[LogiBlox]
show_pinbus_names=YES

[Flow]
FSM_X6=On

[EXTENSIONS]
;XABELNETLIST=PLUSASM
;XABELNETLIST=PLUSASM
InitDialog=On
LastDirectory=C:\FNDTN\ACTIVE\PROJECTS
;XABELNETLIST=PLUSASM
;XABELNETLIST=PLUSASM
UseServerTime=1
disable_exit_dialog=On

[Synthesis]
Exemplar=NO
Asyl=NO
internal_VHDL_check=NO

[Suspro]
Netkey=0
Active=16
Key=5
KeyEx=H9B1CABABABACEB9CABABABABABABABAHEBAB1HABABABABAWAKGL1M9R9M9T9L1BUBUBABABABABABA

[Pcm]
type=F21i

[xilinx]
family=2
xfam=XC4000XL
libraries=unified

[ABEL]
ActiveSim=Off
ViewFiles=On

[AVHDL]
AVHDL_REG_KEY=SOFTWARE\Aldec\Active HDL 4.0\Shared\InstallDir

[UserData]
User=Dave Vanden Bout
Company=XESS Corporation

[Library_List]
1001=C:\FNDTN\ACTIVE\PROJECTS\LEDREG\LIB\LEDREG
171=D:\FNDTN\ACTIVE\SYSLIB\VIRTEX
169=D:\FNDTN\ACTIVE\SYSLIB\SPARTANX
1002=C:\FNDTN\ACTIVE\PROJECTS\RANDGEN\LIB\RANDGEN
1003=D:\FNDTN\ACTIVE\PROJECTS\ONOR2\LIB\ONOR2
1004=D:\FNDTN\ACTIVE\PROJECTS\ONORTST\LIB\ONORTST
1005=D:\FNDTN\ACTIVE\PROJECTS\PARITY\LIB\PARITY
1006=D:\FNDTN\ACTIVE\PROJECTS\INVTEST\LIB\INVTEST
1007=D:\FNDTN\ACTIVE\PROJECTS\LEDREG\LIB\LEDREG
1008=D:\FNDTN\ACTIVE\PROJECTS\RANDGEN\LIB\RANDGEN
153=C:\FNDTN\ACTIVE\SYSLIB\XC4000E
155=C:\FNDTN\ACTIVE\SYSLIB\XC4000X
161=C:\FNDTN\ACTIVE\SYSLIB\XC9500
133=C:\FNDTN\ACTIVE\SYSLIB\SIMPRIMS
149=C:\FNDTN\ACTIVE\SYSLIB\XABELSIM
167=C:\FNDTN\ACTIVE\SYSLIB\SPARTAN

[device]
part=4005XLPC84-3
xilinx=4005XLPC84-3

[dpm32]
DefFreq=50

[PCM_Window]
Left=268
Top=36
Width=600
Height=552
Maximized=Off
LeftWidth=176
UpHeight=296
Settings=On

[Interactive]
Options=1, 1, 1, 1, 0, 0, 0, 2, 1, 1, 0, 0
Logfile=C:\FNDTN\ACTIVE\PROJECTS\ALDEC.LOG
Lines=200
Colors=16711935,255,16711680,0,0,0,0,0,
View=1,0
Console=0, 0, 0, 0, 0, 0, 0, , 0, 0
Errors=0, 0, 0, 0, 0, 0, 0, , 0, 0
Warnings=0, 0, 0, 0, 0, 0, 0, , 0, 0
Messages=0, 0, 0, 0, 0, 0, 0, , 0, 0

[TOOLBOXES]
CHANGES=HIDE 924 50 50 132
SYMBOLS=HIDE 898 113 130 390
WIRES=HIDE 924 50 50 132
GRAPHICS=HIDE 852 50 122 60
PROBES=HIDE 876 50 98 60
QUERY=HIDE 749 10 225 271
VHE=HIDE 924 50 50 108

[LM]
bDelLib=YES
bDetLib=YES
bDelObj=YES
bLibSrc=YES
bObjSrc=YES

[Netlist]
ExpFormat=Edif 200

[HDESettings]
Tabulation=8
Highlighting=1
LineNumbers=1
Margin=1
AutoIndent=1
AutoScanning=1
ErrorsDesciption=0
Language=VHDL
Compiler=METAMOR
Font=0,0,0,0,0,0,0,0,0,0,0,0,0,Fixedsys
ShowPropFonts=1
WorkingDir=D:\Fndtn\Active\Projects\onortst\

[HDEColors]
NormalCol=0
CommentCol=6
KeywordCol=4
ConstantCol=8
DirectivesCol=2
MetaSymbolCol=0

[HDELA2]
State=0
Mode=1
WT=130
WB=396
WR=549
WL=92
TT=2
TB=211
TR=224
TL=2
PT=2
PB=211
PR=449
PL=227

[HDE Recent File List]
File1=D:\FNDTN\ACTIVE\PROJECTS\PARITY\parity8.vhd
File2=D:\Fndtn\Active\Projects\onortst\onor.vhd
File3=d:\fndtn\active\projects\onortst\onor2.vhd
File4=D:\FNDTN\ACTIVE\PROJECTS\ONOR2\onor2.vhd

[Simulator]
main=CONF_MAXMIZE, 44, 44, 768, 537
toolbox=CONF_POSITION, 44, 0, 0, 0
showhier=CONF_HIDE, 0, 0, 0, 0
tv0=CONF_NORMAL, 0, 0, 534, 301, 50, 56
Step=500
Binary Counter=Off
Status Bar=On
Ruler=On
End of Step Estimation=On
Breakpoints Enabled=Off
Prompt for Browsing Netlist Log=On
Prompt for Loading Last Session=On
Display Hidden Nets=Off
Backup Frequency=300
Backup=On
Netlist Log Messages=All
Error Reporting Options=9CE7
External Editor=C:\FNDTN\ACTIVE\EXE\MACROED.EXE

[Pin Parameters]
PINTYPE=
PORT_ID=

[Symbol Parameters]
DEVICE=
LEVEL=
LIBVER=
LOC=
$FILE=
$DEF=
BUS_WIDTH=
DEPTH=
STYLE=
USE_RPM=
DEF=
MODTYPE=
$BUSDELIMITER=
BLKNM=
DIVIDE1_BY=
DIVIDE2_BY=
FAST=
INIT=
NODELAY=
PWR_MODE=
RLOC=
SLOW=
TNM=
$FILE=
$DEF=
BLKNM=
DIVIDE1_BY=
DIVIDE2_BY=
FAST=
INIT=
LEVEL=
LIBVER=
LOC=
NODELAY=
PWR_MODE=
RLOC=
SLOW=
TNM=

[Projects List]
c:\fndtn\active\projects\ledreg=ledreg
c:\fndtn\active\projects\randgen=randgen

[Recent Projects]
c:\fndtn\active\projects\ledreg.pdf=
c:\fndtn\active\projects\randgen.pdf=