isim.log

xilinx 器件vhdl原程序

 command line:
   D:\Stuffz\VHDL\Test_LCD\LCD_Controller_tbw_tbxr.exe
     -intstyle  ise
     -tclbatch  genExpectedResults.cmd

Sun Jul 15 23:26:01 2007

Total Line Count = 974

 Elaboration time 0.015625 sec.

 Estimate current memory usage 33.8944 Meg. 

 Total signals 36
 Total nets 134
 Total signal drivers 30
 Total blocks 7
 Total primitive blocks 1
 Total processes 32
isim batch on 
run all 
Simulator is doing circuit initialization process.
Finished circuit initialization process.
quit 

 Simulation time 0.09375 sec.

 Estimate current memory usage 38.0887 Meg. 

Sun Jul 15 23:26:01 2007