lcd_controller.vhd

xilinx 器件vhdl原程序

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:59:20 07/08/2007 
-- Design Name: 
-- Module Name:    LCD_Controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LCD_Controller is
    Port ( Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           RS : out  STD_LOGIC;
           Data : out  STD_LOGIC_VECTOR (7 downto 0);
           E : out  STD_LOGIC);
end LCD_Controller;

architecture Behavioral of LCD_Controller is
-- 16 state FSM.
type statetype is (	Pwr_Up, Pwr_Up_Delay, Off_Pwr_Up_Delay, Write_Data,
							Data_Setup_Delay, E_Pulse_Hi, E_Hi_Time, E_Pulse_Lo,
							Proc_Comp_Delay, Load_Next_Data, End_State, End_Pad_12,
							End_Pad_13, End_Pad_14, End_Pad_15, End_Pad_16				);
signal State, Next_State: statetype := Pwr_Up;

-- Instruction Counter.
signal Inst_Cnt: STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal Inst_Cnt_E: STD_LOGIC;
signal Data_RS_Bus: STD_LOGIC_VECTOR(8 downto 0);

-- *** Delay Elements.
-- Individual Delay Control.
signal Ind_Delay_Ctrl: STD_LOGIC_VECTOR(3 downto 0);
signal Delay_Switch_Out: STD_LOGIC_VECTOR(3 downto 0);
signal Delay_TO: STD_LOGIC;

-- 45ms Delay.
signal Delay_45ms_E: STD_LOGIC := '0';
signal Delay_45ms: STD_LOGIC_VECTOR (20 downto 0) := "000000000000000000000";

-- 4ms Delay.
signal Delay_4ms_E: STD_LOGIC := '0';
signal Delay_4ms_I: STD_LOGIC := '0';
signal Delay_4ms: STD_LOGIC_VECTOR (17 downto 0) := "000000000000000000";

-- 2ms Delay.
signal Delay_2ms_E: STD_LOGIC := '0';
signal Delay_2ms_I: STD_LOGIC := '0';
signal Delay_2ms: STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";

-- 100us Delay.
signal Delay_100us_E: STD_LOGIC := '0';
signal Delay_100us_I: STD_LOGIC := '0';
signal Delay_100us: STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";

-- 40us Delay.
signal Delay_40us_E: STD_LOGIC := '0';
signal Delay_40us_I: STD_LOGIC := '0';
signal Delay_40us: STD_LOGIC_VECTOR (10 downto 0) := "00000000000";

-- 240ns Delay.
signal Delay_240ns_E: STD_LOGIC := '0';
signal Delay_240ns: STD_LOGIC_VECTOR (3 downto 0) := "0000";

-- 80ns Delay.
signal Delay_80ns_E: STD_LOGIC := '0';
signal Delay_80ns: STD_LOGIC_VECTOR (1 downto 0) := "00";
			
begin
---------------------------------------------------------------------------------------------
-- Power Up Delay.
---------------------------------------------------------------------------------------------
-- Power Up Delay Switch.
process (State)
begin
   if ((State = Pwr_Up) or (State = Pwr_Up_Delay)) then
		Delay_45ms_E <= '1';
   else
		Delay_45ms_E <= '0';
   end if;
end process;

-- 45ms Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_45ms <= "000000000000000000000";
      else
			if (Delay_45ms_E = '1') then
				Delay_45ms <= Delay_45ms + 1;
			end if;
      end if;
   end if;
end process;
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
-- Instruction Counter.
---------------------------------------------------------------------------------------------
-- Instruction Counter Chip Enable Toggle.
process (State)
begin
   if (State = Load_Next_Data) then
		Inst_Cnt_E <= '1';
   else
		Inst_Cnt_E <= '0';
   end if;
end process;

-- Instruction Counter.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
         Inst_Cnt <= "0000";
      else
			if (Inst_Cnt_E = '1') then
				Inst_Cnt <= Inst_Cnt + 1;
			end if;
      end if;
   end if;
end process;

-- Instruction/Data Set with RS bit.
process (Inst_Cnt)
begin
   case (Inst_Cnt) is 
      when "0000" => Data_RS_Bus <= '0' & x"38";
      when "0001" => Data_RS_Bus <= '0' & x"38";
      when "0010" => Data_RS_Bus <= '0' & x"38";
      when "0011" => Data_RS_Bus <= '0' & x"38";
      when "0100" => Data_RS_Bus <= '0' & x"0f";
      when "0101" => Data_RS_Bus <= '0' & x"01";
      when "0110" => Data_RS_Bus <= '0' & x"06";
      when "0111" => Data_RS_Bus <= '1' & x"48";
      when "1000" => Data_RS_Bus <= '1' & x"65";
      when "1001" => Data_RS_Bus <= '1' & x"6c";
      when "1010" => Data_RS_Bus <= '1' & x"6c";
      when "1011" => Data_RS_Bus <= '1' & x"6f";
      when "1100" => Data_RS_Bus <= '1' & x"20";
      when "1101" => Data_RS_Bus <= '1' & x"61";
      when "1110" => Data_RS_Bus <= '1' & x"6c";
      when others => Data_RS_Bus <= '1' & x"6c";
   end case;
end process;

-- Route Data_RS_Bus to RS and Data bus on the LCD.
RS <= Data_RS_Bus(8);
Data <= Data_RS_Bus(7 downto 0);
			
---------------------------------------------------------------------------------------------
-- Bulk Delay Control.
---------------------------------------------------------------------------------------------
-- Delay Controller.
process (Inst_Cnt)
begin
   case (Inst_Cnt) is 
      when "0000" => Ind_Delay_Ctrl <= "1000";
      when "0001" => Ind_Delay_Ctrl <= "0010";
      when "0010" => Ind_Delay_Ctrl <= "0001";
      when "0011" => Ind_Delay_Ctrl <= "0001";
      when "0100" => Ind_Delay_Ctrl <= "0001";
      when "0101" => Ind_Delay_Ctrl <= "0100";
      when "0110" => Ind_Delay_Ctrl <= "0001";
      when "0111" => Ind_Delay_Ctrl <= "0001";
      when "1000" => Ind_Delay_Ctrl <= "0001";
      when "1001" => Ind_Delay_Ctrl <= "0001";
      when "1010" => Ind_Delay_Ctrl <= "0001";
      when "1011" => Ind_Delay_Ctrl <= "0001";
      when "1100" => Ind_Delay_Ctrl <= "0001";
      when "1101" => Ind_Delay_Ctrl <= "0001";
      when "1110" => Ind_Delay_Ctrl <= "0001";
      when others => Ind_Delay_Ctrl <= "0001";
   end case;
end process;

-- Delay Switch.
process (State, Ind_Delay_Ctrl)
begin
   if ((State = E_Pulse_Lo) or (State = Proc_Comp_Delay)) then
		Delay_Switch_Out <= Ind_Delay_Ctrl;
   else
		Delay_Switch_Out <= "0000";
   end if;
end process;

-- Wiring to each CE signals.
Delay_4ms_E <= Delay_Switch_Out(3);
Delay_2ms_E <= Delay_Switch_Out(2);
Delay_100us_E <= Delay_Switch_Out(1);
Delay_40us_E <= Delay_Switch_Out(0);
			
-- 4ms Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_4ms <= "000000000000000000";
      else
			if (Delay_4ms_E = '1') then
				Delay_4ms <= Delay_4ms + 1;
			end if;
      end if;
   end if;
end process;

-- 4ms Delay Timeout Indicator.
process (Delay_4ms)
begin
   if (Delay_4ms = "111111111111111111") then
		Delay_4ms_I <= '1';
	else
		Delay_4ms_I <= '0';
	end if;
end process;

-- 2ms Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_2ms <= "00000000000000000";
      else
			if (Delay_2ms_E = '1') then
				Delay_2ms <= Delay_2ms + 1;
			end if;
      end if;
   end if;
end process;

-- 2ms Delay Timeout Indicator.
process (Delay_2ms)
begin
   if (Delay_2ms = "11111111111111111") then
		Delay_2ms_I <= '1';
	else
		Delay_2ms_I <= '0';
	end if;
end process;

-- 100us Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_100us <= "0000000000000";
      else
			if (Delay_100us_E = '1') then
				Delay_100us <= Delay_100us + 1;
			end if;
      end if;
   end if;
end process;

-- 100us Delay Timeout Indicator.
process (Delay_100us)
begin
   if (Delay_100us = "11111111111") then
		Delay_100us_I <= '1';
	else
		Delay_100us_I <= '0';
	end if;
end process;

-- 40us Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_40us <= "00000000000";
      else
			if (Delay_40us_E = '1') then
				Delay_40us <= Delay_40us + 1;
			end if;
      end if;
   end if;
end process;

-- 40us Delay Timeout Indicator.
process (Delay_40us)
begin
   if (Delay_40us = "11111111111") then
		Delay_40us_I <= '1';
	else
		Delay_40us_I <= '0';
	end if;
end process;

-- Delay Timeout Selector.
process (Inst_Cnt, Delay_4ms_I, Delay_2ms_I, Delay_100us_I, Delay_40us_I)
begin
   case (Inst_Cnt) is 
      when "0000" => Delay_TO <= Delay_4ms_I;
      when "0001" => Delay_TO <= Delay_100us_I;
      when "0010" => Delay_TO <= Delay_40us_I;
      when "0011" => Delay_TO <= Delay_40us_I;
      when "0100" => Delay_TO <= Delay_40us_I;
      when "0101" => Delay_TO <= Delay_2ms_I;
      when "0110" => Delay_TO <= Delay_40us_I;
      when "0111" => Delay_TO <= Delay_40us_I;
      when "1000" => Delay_TO <= Delay_40us_I;
      when "1001" => Delay_TO <= Delay_40us_I;
      when "1010" => Delay_TO <= Delay_40us_I;
      when "1011" => Delay_TO <= Delay_40us_I;
      when "1100" => Delay_TO <= Delay_40us_I;
      when "1101" => Delay_TO <= Delay_40us_I;
      when "1110" => Delay_TO <= Delay_40us_I;
      when others => Delay_TO <= Delay_40us_I;
   end case;
end process;
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
-- Enable Pulse Generation.
---------------------------------------------------------------------------------------------
-- 80ns Delay Chip Enable Toggle.
process (State)
begin
   if ((State = Write_Data) or (State = Data_Setup_Delay)) then
		Delay_80ns_E <= '1';
   else
		Delay_80ns_E <= '0';
   end if;
end process;

-- 80ns Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_80ns <= "00";
      else
			if (Delay_80ns_E = '1') then
				Delay_80ns <= Delay_80ns + 1;
			end if;
      end if;
   end if;
end process;

-- 240ns Delay Chip Enable Toggle.
process (State)
begin
   if ((State = E_Pulse_Hi) or (State = E_Hi_Time)) then
		Delay_240ns_E <= '1';
   else
		Delay_240ns_E <= '0';
   end if;
end process;

-- 240ns Delay Chip Enable Toggle.
process (State)
begin
   if ((State = E_Pulse_Hi) or (State = E_Hi_Time)) then
		E <= '1';
   else
		E <= '0';
   end if;
end process;

-- 240ns Delay Element.
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
			Delay_240ns <= "0000";
      else
			if (Delay_240ns_E = '1') then
				Delay_240ns <= Delay_240ns + 1;
			end if;
      end if;
   end if;
end process;
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
-- State switcher.
---------------------------------------------------------------------------------------------
process (Clk)
begin  
   if (Clk'event and Clk = '1') then
      if Reset = '1' then
         State <= Pwr_Up;
      else
			State <= Next_State;
      end if;
   end if;
end process;
---------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
-- State machine => Updates the next state.
---------------------------------------------------------------------------------------------
process (State, Delay_45ms, Delay_80ns, Delay_240ns, Delay_TO, Inst_Cnt)
begin

	case (State) is 
		when Pwr_Up =>
			Next_State <= Pwr_Up_Delay;
			
		when Pwr_Up_Delay =>
			if (Delay_45ms = "111111111111111111111") then
				Next_State <= Off_Pwr_Up_Delay;
			else
				Next_State <= Pwr_Up_Delay;
			end if;
		
		when Off_Pwr_Up_Delay =>
			Next_State <= Write_Data;
		
		when Write_Data =>
			Next_State <= Data_Setup_Delay;
		
		when Data_Setup_Delay =>
			if (Delay_80ns = "11") then
				Next_State <= E_Pulse_Hi;
			else
				Next_State <= Data_Setup_Delay;
			end if;
				
		when E_Pulse_Hi =>
			Next_State <= E_Hi_Time;
			
		when E_Hi_Time =>
			if (Delay_240ns = "1111") then
				Next_State <= E_Pulse_Lo;
			else
				Next_State <= E_Hi_Time;
			end if;
		
		when E_Pulse_Lo =>
			Next_State <= Proc_Comp_Delay;
		
		when Proc_Comp_Delay =>
			if (Delay_TO = '1') then
				Next_State <= Load_Next_Data;
			else
				Next_State <= Proc_Comp_Delay;
			end if;
			
		when Load_Next_Data =>
			if (Inst_Cnt = "1111") then
				Next_State <= End_State;
			else
				Next_State <= Write_Data;
			end if;
				
		when End_State =>
			Next_State <= End_Pad_12;
			
		when End_Pad_12 =>
			Next_State <= End_Pad_13;
			
		when End_Pad_13 =>
			Next_State <= End_Pad_14;
			
		when End_Pad_14 =>
			Next_State <= End_Pad_15;
		
		when End_Pad_15 =>
			Next_State <= End_Pad_16;
			
		when End_Pad_16 =>
			Next_State <= End_Pad_16;

	end case;
end process;
---------------------------------------------------------------------------------------------
				
end Behavioral;