notetabs.vhd

正弦波VHDL语言~~~ ~~~ ~~~ ~~~`

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity notetabs is
port(clk:IN std_logic;
     Toneindex:out std_logic_vector(9 downto 0));
end notetabs;
architecture one of notetabs is
signal counter:integer range 0 to 63;  --63个数
signal dout:integer range 0000 to 1023;
begin
cnt8:process(clk,counter)
begin
   if (counter=60) then counter<=0;
elsif (clk'event and clk='1') then counter<=counter+1;
end if;
end process;
Search:process(counter)
begin
case counter is

when 00=>dout<=0000;when 01=>dout<=0001;
when 02=>dout<=0002;when 03=>dout<=0003;
when 04=>dout<=0004;when 05=>dout<=0005;
when 06=>dout<=0006;when 07=>dout<=0007;
when 08=>dout<=0008;when 09=>dout<=0009;
when 10=>dout<=0010;when 11=>dout<=0011;
when 12=>dout<=0012;when 13=>dout<=0013;
when 14=>dout<=0014;when 15=>dout<=0015;
when 16=>dout<=0016;when 17=>dout<=0017;
when 18=>dout<=0018;when 19=>dout<=0019;
when 20=>dout<=0020;when 21=>dout<=0021;
when 22=>dout<=0022;when 23=>dout<=0023;
when 24=>dout<=0024;when 25=>dout<=0025;
when 26=>dout<=0026;when 27=>dout<=0027;
when 28=>dout<=0028;when 29=>dout<=0029;
when 30=>dout<=0030;when 31=>dout<=0031;
when 32=>dout<=0032;when 33=>dout<=0033;
when 34=>dout<=0034;when 35=>dout<=0035;
when 36=>dout<=0036;when 37=>dout<=0037;
when 38=>dout<=0038;when 39=>dout<=0039;
when 40=>dout<=0040;when 41=>dout<=0041;
when 42=>dout<=0042;when 43=>dout<=0043;
when 44=>dout<=0044;when 45=>dout<=0045;
when 46=>dout<=0046;when 47=>dout<=0047;
when 48=>dout<=0048;when 49=>dout<=0049;
when 50=>dout<=0050;when 51=>dout<=0051;
when 52=>dout<=0052;when 53=>dout<=0053;
when 54=>dout<=0054;when 55=>dout<=0055;
when 56=>dout<=0056;when 57=>dout<=0057;
when 58=>dout<=0058;when 59=>dout<=0059;
when 60=>dout<=0060;when 61=>dout<=0061;
when 62=>dout<=0062;when 63=>dout<=0063;
when others=>dout<=0000;
end case;
end process;
toneindex<=conv_std_logic_vector(dout,10);
end one;