pulse_sum.hier_info

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

|pulse_sum
Reset => pulse_out~15.OUTPUTSELECT
Reset => always0~0.IN0
Clock_65536Hz => pulse_1~1.IN0
Clock_65536Hz => pulse_1~3.IN0
Clock_65536Hz => pulse_1~5.IN0
Clock_65536Hz => pulse_1~7.IN0
Clock_65536Hz => pulse_1~9.IN0
Clock_65536Hz => pulse_1~11.IN0
Clock_65536Hz => pulse_1~13.IN0
Clock_65536Hz => pulse_1~15.IN0
Clock_65536Hz => pulse_1~17.IN0
Clock_65536Hz => pulse_1~19.IN0
Clock_65536Hz => pulse_1~21.IN0
Clock_65536Hz => pulse_1~23.IN0
Clock_65536Hz => pulse_1~25.IN0
Clock_65536Hz => pulse_1~27.IN0
Clock_65536Hz => pulse_1~29.IN0
Clock_65536Hz => pulse_1~31.IN0
pulse_16_data[0] => pulse_1~0.IN0
pulse_16_data[1] => pulse_1~2.IN0
pulse_16_data[2] => pulse_1~4.IN0
pulse_16_data[3] => pulse_1~6.IN0
pulse_16_data[4] => pulse_1~8.IN0
pulse_16_data[5] => pulse_1~10.IN0
pulse_16_data[6] => pulse_1~12.IN0
pulse_16_data[7] => pulse_1~14.IN0
pulse_16_data[8] => pulse_1~16.IN0
pulse_16_data[9] => pulse_1~18.IN0
pulse_16_data[10] => pulse_1~20.IN0
pulse_16_data[11] => pulse_1~22.IN0
pulse_16_data[12] => pulse_1~24.IN0
pulse_16_data[13] => pulse_1~26.IN0
pulse_16_data[14] => pulse_1~28.IN0
pulse_16_data[15] => pulse_1~30.IN0
second_pulse_data[0] => pulse_1~0.IN1
second_pulse_data[1] => pulse_1~2.IN1
second_pulse_data[2] => pulse_1~4.IN1
second_pulse_data[3] => pulse_1~6.IN1
second_pulse_data[4] => pulse_1~8.IN1
second_pulse_data[5] => pulse_1~10.IN1
second_pulse_data[6] => pulse_1~12.IN1
second_pulse_data[7] => pulse_1~14.IN1
second_pulse_data[8] => pulse_1~16.IN1
second_pulse_data[9] => pulse_1~18.IN1
second_pulse_data[10] => pulse_1~20.IN1
second_pulse_data[11] => pulse_1~22.IN1
second_pulse_data[12] => pulse_1~24.IN1
second_pulse_data[13] => pulse_1~26.IN1
second_pulse_data[14] => pulse_1~28.IN1
second_pulse_data[15] => pulse_1~30.IN1
pulse_out <= pulse_out~15.DB_MAX_OUTPUT_PORT_TYPE