counter_16_bits.fit.summary

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

Flow Status : Successful - Wed Jul 19 20:36:40 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : counter_16_bits
Top-level Entity Name : counter_16_bits
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 16 / 32 ( 50 % )
Total pins : 22 / 36 ( 61 % )
Device : EPM7032SLC44-5
Timing Models : Final